From: Jisheng Zhang <Jisheng.Zhang@synaptics.com> To: Jon Hunter <jonathanh@nvidia.com> Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>, Neil Armstrong <narmstrong@baylibre.com>, linux-pci@vger.kernel.org, Binghui Wang <wangbinghui@hisilicon.com>, Bjorn Andersson <bjorn.andersson@linaro.org>, Masahiro Yamada <yamada.masahiro@socionext.com>, Thierry Reding <thierry.reding@gmail.com>, linux-arm-kernel@axis.com, Vidya Sagar <vidyas@nvidia.com>, Fabio Estevam <festevam@gmail.com>, Jerome Brunet <jbrunet@baylibre.com>, Rob Herring <robh@kernel.org>, Jesper Nilsson <jesper.nilsson@axis.com>, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>, Kevin Hilman <khilman@baylibre.com>, Pratyush Anand <pratyush.anand@gmail.com>, linux-tegra@vger.kernel.org, Krzysztof Kozlowski <krzk@kernel.org>, Kishon Vijay Abraham I <kishon@ti.com>, Kukjin Kim <kgene@kernel.org>, NXP Linux Team <linux-imx@nxp.com>, Xiaowei Song <songxiaowei@hisilicon.com>, Richard Zhu <hongxing.zhu@nxp.com>, Martin Blumenstingl <martin.blumenstingl@googlemail.com>, linux-arm-msm@vger.kernel.org, Sascha Hauer <s.hauer@pengutronix.de>, Yue Wang <yue.wang@Amlogic.com>, linux-samsung-soc@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>, linux-amlogic@lists.infradead.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jingoo Han <jingoohan1@gmail.com>, Andy Gross <agross@kernel.org>, linux-kernel@vger.kernel.org, Stanimir Varbanov <svarbanov@mm-sol.com>, Pengutronix Kernel Team <kernel@pengutronix.de>, Gustavo Pimentel <gustavo.pimentel@synopsys.com>, Shawn Guo <shawnguo@kernel.org>, Lucas Stach <l.stach@pengutronix.de> Subject: Re: [PATCH v2 0/5] PCI: dwc: improve msi handling Date: Fri, 25 Sep 2020 17:27:24 +0800 [thread overview] Message-ID: <20200925172724.5bdf6aab@xhacker.debian> (raw) In-Reply-To: <20200925171712.254a018d@xhacker.debian> On Fri, 25 Sep 2020 17:17:12 +0800 Jisheng Zhang <Jisheng.Zhang@synaptics.com> wrote: > CAUTION: Email originated externally, do not click links or open attachments unless you recognize the sender and know the content is safe. > > > Hi Jon, > > On Fri, 25 Sep 2020 09:53:45 +0100 Jon Hunter wrote: > > > > > > On 24/09/2020 12:05, Jisheng Zhang wrote: > > > Improve the msi code: > > > 1. Add proper error handling. > > > 2. Move dw_pcie_msi_init() from each users to designware host to solve > > > msi page leakage in resume path. > > > > Apologies if this is slightly off topic, but I have been meaning to ask > > about MSIs and PCI. On Tegra194 which uses the DWC PCI driver, whenever we > > hotplug CPUs we see the following warnings ... > > > > [ 79.068351] WARNING KERN IRQ70: set affinity failed(-22). > > [ 79.068362] WARNING KERN IRQ71: set affinity failed(-22). > > > > These interrupts are the MSIs ... > > > > 70: 0 0 0 0 0 0 0 0 PCI-MSI 134217728 Edge PCIe PME, aerdrv > > 71: 0 0 0 0 0 0 0 0 PCI-MSI 134742016 Edge ahci[0001:01:00.0] > > > > This caused because ... > > > > static int dw_pci_msi_set_affinity(struct irq_data *d, > > const struct cpumask *mask, bool force) > > { > > return -EINVAL; > > } > > > > Now the above is not unique to the DWC PCI host driver, it appears that > > most PCIe drivers also do the same. However, I am curious if there is > > any way to avoid the above warnings given that setting the affinity does > > not appear to be supported in anyway AFAICT. > > > > > Could you please try below patch? > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index bf25d783b5c5..7e5dc54d060e 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -197,7 +197,6 @@ static struct irq_chip dw_pci_msi_bottom_irq_chip = { > .name = "DWPCI-MSI", > .irq_ack = dw_pci_bottom_ack, > .irq_compose_msi_msg = dw_pci_setup_msi_msg, > - .irq_set_affinity = dw_pci_msi_set_affinity, > .irq_mask = dw_pci_bottom_mask, > .irq_unmask = dw_pci_bottom_unmask, > }; A complete patch w/o compiler warning: diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index bf25d783b5c5..18f719cfed0b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -137,12 +137,6 @@ static void dw_pci_setup_msi_msg(struct irq_data *d, struct msi_msg *msg) (int)d->hwirq, msg->address_hi, msg->address_lo); } -static int dw_pci_msi_set_affinity(struct irq_data *d, - const struct cpumask *mask, bool force) -{ - return -EINVAL; -} - static void dw_pci_bottom_mask(struct irq_data *d) { struct pcie_port *pp = irq_data_get_irq_chip_data(d); @@ -197,7 +191,6 @@ static struct irq_chip dw_pci_msi_bottom_irq_chip = { .name = "DWPCI-MSI", .irq_ack = dw_pci_bottom_ack, .irq_compose_msi_msg = dw_pci_setup_msi_msg, - .irq_set_affinity = dw_pci_msi_set_affinity, .irq_mask = dw_pci_bottom_mask, .irq_unmask = dw_pci_bottom_unmask, };
next prev parent reply other threads:[~2020-09-25 9:28 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-24 11:05 Jisheng Zhang 2020-09-24 11:05 ` [PATCH v2 1/5] PCI: dwc: Call dma_unmap_page() before freeing the msi page Jisheng Zhang 2020-09-24 11:48 ` Gustavo Pimentel 2020-09-24 11:06 ` [PATCH v2 2/5] PCI: dwc: Check alloc_page() return value Jisheng Zhang 2020-09-24 11:47 ` Gustavo Pimentel 2020-09-29 17:29 ` Marc Zyngier 2020-09-30 1:23 ` Jisheng Zhang 2020-09-24 11:06 ` [PATCH v2 3/5] PCI: dwc: Rename dw_pcie_free_msi to dw_pcie_msi_deinit Jisheng Zhang 2020-09-24 11:49 ` Gustavo Pimentel 2020-09-24 11:07 ` [PATCH v2 4/5] PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabled Jisheng Zhang 2020-09-24 11:49 ` Gustavo Pimentel 2020-09-24 11:07 ` [PATCH v2 5/5] PCI: dwc: Move dw_pcie_msi_init() from each users to designware host Jisheng Zhang 2020-10-08 5:43 ` Vidya Sagar 2021-03-07 22:10 ` Krzysztof Wilczyński 2021-03-11 6:50 ` Jisheng Zhang 2020-09-25 8:53 ` [PATCH v2 0/5] PCI: dwc: improve msi handling Jon Hunter 2020-09-25 9:17 ` Jisheng Zhang 2020-09-25 9:27 ` Jisheng Zhang [this message] 2020-09-25 15:13 ` Jon Hunter 2020-09-27 8:28 ` Jisheng Zhang 2020-09-28 17:46 ` Jon Hunter 2020-09-29 10:48 ` Jisheng Zhang 2020-09-29 13:22 ` Jon Hunter 2020-09-29 17:25 ` Marc Zyngier 2020-09-29 18:02 ` Jon Hunter 2020-09-29 18:12 ` Marc Zyngier 2020-10-06 6:26 ` Vidya Sagar 2020-10-06 6:36 ` Jisheng Zhang 2020-10-08 5:32 ` Vidya Sagar 2020-10-09 8:37 ` [PATCH] PCI: dwc: Move dw_pcie_msi_init() from each users to designware host Jisheng Zhang
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