* [PATCH 0/2] Add Mailbox support for TI K3 AM64x SoCs @ 2021-01-27 19:55 Suman Anna 2021-01-27 19:55 ` [PATCH 1/2] dt-bindings: mailbox: omap: Update binding for " Suman Anna 2021-01-27 19:56 ` [PATCH 2/2] mailbox: omap: Add support for K3 " Suman Anna 0 siblings, 2 replies; 5+ messages in thread From: Suman Anna @ 2021-01-27 19:55 UTC (permalink / raw) To: Jassi Brar, Rob Herring Cc: devicetree, linux-omap, linux-arm-kernel, linux-kernel, Suman Anna Hi Jassi, The following series extends the OMAP Mailbox driver to enable the Mailbox IP present on the most recent TI K3 AM64x SoCs [1]. AM64x is a 64-bit system, and the Mailbox IP is a cut-down version of the one present on previous TI K3 SoCs like AM65x and J721E. DT nodes will be posted separately once the binding is acked/merged. regards Suman [1] https://patchwork.kernel.org/project/linux-arm-kernel/cover/20210120202532.9011-1-d-gerlach@ti.com/ Suman Anna (2): dt-bindings: mailbox: omap: Update binding for AM64x SoCs mailbox: omap: Add support for K3 AM64x SoCs .../bindings/mailbox/omap-mailbox.txt | 22 +++++++++++++++++++ drivers/mailbox/omap-mailbox.c | 6 ++++- 2 files changed, 27 insertions(+), 1 deletion(-) -- 2.29.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] dt-bindings: mailbox: omap: Update binding for AM64x SoCs 2021-01-27 19:55 [PATCH 0/2] Add Mailbox support for TI K3 AM64x SoCs Suman Anna @ 2021-01-27 19:55 ` Suman Anna 2021-02-09 19:24 ` Rob Herring 2021-01-27 19:56 ` [PATCH 2/2] mailbox: omap: Add support for K3 " Suman Anna 1 sibling, 1 reply; 5+ messages in thread From: Suman Anna @ 2021-01-27 19:55 UTC (permalink / raw) To: Jassi Brar, Rob Herring Cc: devicetree, linux-omap, linux-arm-kernel, linux-kernel, Suman Anna Update the existing OMAP Mailbox binding to include the info for AM64x SoCs. There are some minor IP integration differences between the AM64x SoCs and the previous AM65x and J721E SoC families. Signed-off-by: Suman Anna <s-anna@ti.com> --- .../bindings/mailbox/omap-mailbox.txt | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt index 5fe80c1c19fc..c993d1a5c14a 100644 --- a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt +++ b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt @@ -28,6 +28,9 @@ SoCs has each of these instances form a cluster and combine multiple clusters into a single IP block present within the Main NavSS. The interrupt lines from all these clusters are multiplexed and routed to different processor subsystems over a limited number of common interrupt output lines of an Interrupt Router. +The AM64x SoCS also uses a single IP block comprising of multiple clusters, +but the number of clusters are smaller, and the interrupt output lines are +connected directly to various processors. Mailbox Device Node: ==================== @@ -42,6 +45,7 @@ Required properties: "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx, AM43xx and DRA7xx SoCs "ti,am654-mailbox" for K3 AM65x and J721E SoCs + "ti,am64-mailbox" for K3 AM64x SoCs - reg: Contains the mailbox register address range (base address and length) - interrupts: Contains the interrupt information for the mailbox @@ -178,3 +182,21 @@ mailbox: mailbox@480c8000 { }; }; }; + +4. /* AM64x */ +&cbass_main { + mailbox0_cluster2: mailbox@29020000 { + compatible = "ti,am64-mailbox"; + reg = <0x00 0x29020000 0x00 0x200>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; + }; +}; -- 2.29.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mailbox: omap: Update binding for AM64x SoCs 2021-01-27 19:55 ` [PATCH 1/2] dt-bindings: mailbox: omap: Update binding for " Suman Anna @ 2021-02-09 19:24 ` Rob Herring 2021-02-09 19:26 ` Suman Anna 0 siblings, 1 reply; 5+ messages in thread From: Rob Herring @ 2021-02-09 19:24 UTC (permalink / raw) To: Suman Anna Cc: Jassi Brar, devicetree, linux-omap, linux-arm-kernel, linux-kernel On Wed, Jan 27, 2021 at 01:55:59PM -0600, Suman Anna wrote: > Update the existing OMAP Mailbox binding to include the info for > AM64x SoCs. There are some minor IP integration differences between > the AM64x SoCs and the previous AM65x and J721E SoC families. > > Signed-off-by: Suman Anna <s-anna@ti.com> > --- > .../bindings/mailbox/omap-mailbox.txt | 22 +++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt > index 5fe80c1c19fc..c993d1a5c14a 100644 > --- a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt > +++ b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt > @@ -28,6 +28,9 @@ SoCs has each of these instances form a cluster and combine multiple clusters > into a single IP block present within the Main NavSS. The interrupt lines from > all these clusters are multiplexed and routed to different processor subsystems > over a limited number of common interrupt output lines of an Interrupt Router. > +The AM64x SoCS also uses a single IP block comprising of multiple clusters, > +but the number of clusters are smaller, and the interrupt output lines are > +connected directly to various processors. > > Mailbox Device Node: > ==================== > @@ -42,6 +45,7 @@ Required properties: > "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx, > AM43xx and DRA7xx SoCs > "ti,am654-mailbox" for K3 AM65x and J721E SoCs > + "ti,am64-mailbox" for K3 AM64x SoCs > - reg: Contains the mailbox register address range (base > address and length) > - interrupts: Contains the interrupt information for the mailbox > @@ -178,3 +182,21 @@ mailbox: mailbox@480c8000 { > }; > }; > }; > + > +4. /* AM64x */ > +&cbass_main { Please don't add examples for just a new compatible. > + mailbox0_cluster2: mailbox@29020000 { > + compatible = "ti,am64-mailbox"; > + reg = <0x00 0x29020000 0x00 0x200>; > + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > + #mbox-cells = <1>; > + ti,mbox-num-users = <4>; > + ti,mbox-num-fifos = <16>; > + > + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { > + ti,mbox-rx = <0 0 2>; > + ti,mbox-tx = <1 0 2>; > + }; > + }; > +}; > -- > 2.29.2 > ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] dt-bindings: mailbox: omap: Update binding for AM64x SoCs 2021-02-09 19:24 ` Rob Herring @ 2021-02-09 19:26 ` Suman Anna 0 siblings, 0 replies; 5+ messages in thread From: Suman Anna @ 2021-02-09 19:26 UTC (permalink / raw) To: Rob Herring Cc: Jassi Brar, devicetree, linux-omap, linux-arm-kernel, linux-kernel On 2/9/21 1:24 PM, Rob Herring wrote: > On Wed, Jan 27, 2021 at 01:55:59PM -0600, Suman Anna wrote: >> Update the existing OMAP Mailbox binding to include the info for >> AM64x SoCs. There are some minor IP integration differences between >> the AM64x SoCs and the previous AM65x and J721E SoC families. >> >> Signed-off-by: Suman Anna <s-anna@ti.com> >> --- >> .../bindings/mailbox/omap-mailbox.txt | 22 +++++++++++++++++++ >> 1 file changed, 22 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt >> index 5fe80c1c19fc..c993d1a5c14a 100644 >> --- a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt >> +++ b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt >> @@ -28,6 +28,9 @@ SoCs has each of these instances form a cluster and combine multiple clusters >> into a single IP block present within the Main NavSS. The interrupt lines from >> all these clusters are multiplexed and routed to different processor subsystems >> over a limited number of common interrupt output lines of an Interrupt Router. >> +The AM64x SoCS also uses a single IP block comprising of multiple clusters, >> +but the number of clusters are smaller, and the interrupt output lines are >> +connected directly to various processors. >> >> Mailbox Device Node: >> ==================== >> @@ -42,6 +45,7 @@ Required properties: >> "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx, >> AM43xx and DRA7xx SoCs >> "ti,am654-mailbox" for K3 AM65x and J721E SoCs >> + "ti,am64-mailbox" for K3 AM64x SoCs >> - reg: Contains the mailbox register address range (base >> address and length) >> - interrupts: Contains the interrupt information for the mailbox >> @@ -178,3 +182,21 @@ mailbox: mailbox@480c8000 { >> }; >> }; >> }; >> + >> +4. /* AM64x */ >> +&cbass_main { > > Please don't add examples for just a new compatible. Thanks, will keep this in mind for the future and drop this as well just like on the HwSpinlock binding update. regards Suman > >> + mailbox0_cluster2: mailbox@29020000 { >> + compatible = "ti,am64-mailbox"; >> + reg = <0x00 0x29020000 0x00 0x200>; >> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; >> + #mbox-cells = <1>; >> + ti,mbox-num-users = <4>; >> + ti,mbox-num-fifos = <16>; >> + >> + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { >> + ti,mbox-rx = <0 0 2>; >> + ti,mbox-tx = <1 0 2>; >> + }; >> + }; >> +}; >> -- >> 2.29.2 >> ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] mailbox: omap: Add support for K3 AM64x SoCs 2021-01-27 19:55 [PATCH 0/2] Add Mailbox support for TI K3 AM64x SoCs Suman Anna 2021-01-27 19:55 ` [PATCH 1/2] dt-bindings: mailbox: omap: Update binding for " Suman Anna @ 2021-01-27 19:56 ` Suman Anna 1 sibling, 0 replies; 5+ messages in thread From: Suman Anna @ 2021-01-27 19:56 UTC (permalink / raw) To: Jassi Brar, Rob Herring Cc: devicetree, linux-omap, linux-arm-kernel, linux-kernel, Suman Anna The AM64x SoC contains a Mailbox IP instance with multiple clusters in the MAIN domain, and is a variant of the IP on current AM65x and J721E SoCs. The AM64x SoC has only 8 clusters with no interrupts routed to the A53 core on the first 2 clusters. The interrupt outputs from the IP do not go through any Interrupt Routers and are hard-wired to each processor, with only couple of interrupts from each cluster reaching the A53 core. The IP is also not built with the K3 safety feature in hardware. Add the support for this IP through a new compatible. Signed-off-by: Suman Anna <s-anna@ti.com> --- drivers/mailbox/omap-mailbox.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/omap-mailbox.c b/drivers/mailbox/omap-mailbox.c index 93fe08aef3ca..7295e3835e30 100644 --- a/drivers/mailbox/omap-mailbox.c +++ b/drivers/mailbox/omap-mailbox.c @@ -3,7 +3,7 @@ * OMAP mailbox driver * * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. - * Copyright (C) 2013-2019 Texas Instruments Incorporated - https://www.ti.com + * Copyright (C) 2013-2021 Texas Instruments Incorporated - https://www.ti.com * * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> * Suman Anna <s-anna@ti.com> @@ -663,6 +663,10 @@ static const struct of_device_id omap_mailbox_of_match[] = { .compatible = "ti,am654-mailbox", .data = &omap4_data, }, + { + .compatible = "ti,am64-mailbox", + .data = &omap4_data, + }, { /* end */ }, -- 2.29.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-02-09 20:56 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-01-27 19:55 [PATCH 0/2] Add Mailbox support for TI K3 AM64x SoCs Suman Anna 2021-01-27 19:55 ` [PATCH 1/2] dt-bindings: mailbox: omap: Update binding for " Suman Anna 2021-02-09 19:24 ` Rob Herring 2021-02-09 19:26 ` Suman Anna 2021-01-27 19:56 ` [PATCH 2/2] mailbox: omap: Add support for K3 " Suman Anna
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