* [PATCH 0/4] PCI: Add legacy interrupt support in pci-j721e
@ 2021-03-25 9:09 Kishon Vijay Abraham I
2021-03-25 9:09 ` [PATCH 1/4] dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts Kishon Vijay Abraham I
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Kishon Vijay Abraham I @ 2021-03-25 9:09 UTC (permalink / raw)
To: Kishon Vijay Abraham I, Bjorn Helgaas, Rob Herring,
Lorenzo Pieralisi, Marc Zyngier
Cc: Tom Joseph, linux-omap, linux-pci, devicetree, linux-kernel,
linux-arm-kernel, Lokesh Vutla
Patch series adds support for legacy interrupt in pci-j721e. There are
two HW implementations of legacy interrupt controller, one specific to
J721E and the other for J7200/AM64.
In both these implementations, the legacy interrupt is connect to pulse
interrupt of GIC and level to pulse is handled by configuring EOI
register.
Kishon Vijay Abraham I (4):
dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts
PCI: j721e: Add PCI legacy interrupt support for J721E
PCI: j721e: Add PCIe support for j7200
PCI: j721e: Add PCIe support for AM64
.../bindings/pci/ti,j721e-pci-host.yaml | 13 ++
drivers/pci/controller/cadence/pci-j721e.c | 194 +++++++++++++++++-
2 files changed, 201 insertions(+), 6 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH 1/4] dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts 2021-03-25 9:09 [PATCH 0/4] PCI: Add legacy interrupt support in pci-j721e Kishon Vijay Abraham I @ 2021-03-25 9:09 ` Kishon Vijay Abraham I 2021-03-25 16:56 ` [PATCH 1/4] dt-bindings: PCI: ti, j721e: " Rob Herring 2021-03-25 9:09 ` [PATCH 2/4] PCI: j721e: Add PCI legacy interrupt support for J721E Kishon Vijay Abraham I ` (2 subsequent siblings) 3 siblings, 1 reply; 8+ messages in thread From: Kishon Vijay Abraham I @ 2021-03-25 9:09 UTC (permalink / raw) To: Kishon Vijay Abraham I, Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi, Marc Zyngier Cc: Tom Joseph, linux-omap, linux-pci, devicetree, linux-kernel, linux-arm-kernel, Lokesh Vutla Add bindings to specify interrupt controller for legacy interrupts. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 05aeb1aa362a..3e70a8049eea 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -73,6 +73,11 @@ properties: msi-map: true +patternProperties: + "interrupt-controller": + type: object + description: interrupt controller to handle legacy interrupts. + required: - compatible - reg @@ -130,5 +135,13 @@ examples: ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>, <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; + + + pcie0_intc: interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>; + }; }; }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/4] dt-bindings: PCI: ti, j721e: Add bindings to specify legacy interrupts 2021-03-25 9:09 ` [PATCH 1/4] dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts Kishon Vijay Abraham I @ 2021-03-25 16:56 ` Rob Herring 0 siblings, 0 replies; 8+ messages in thread From: Rob Herring @ 2021-03-25 16:56 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Lorenzo Pieralisi, linux-omap, Tom Joseph, linux-arm-kernel, devicetree, linux-kernel, linux-pci, Bjorn Helgaas, Marc Zyngier, Rob Herring, Lokesh Vutla On Thu, 25 Mar 2021 14:39:33 +0530, Kishon Vijay Abraham I wrote: > Add bindings to specify interrupt controller for legacy interrupts. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Error: Documentation/devicetree/bindings/pci/ti,j721e-pci-host.example.dts:59.39-40 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [scripts/Makefile.lib:349: Documentation/devicetree/bindings/pci/ti,j721e-pci-host.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... make: *** [Makefile:1380: dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1458255 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/4] PCI: j721e: Add PCI legacy interrupt support for J721E 2021-03-25 9:09 [PATCH 0/4] PCI: Add legacy interrupt support in pci-j721e Kishon Vijay Abraham I 2021-03-25 9:09 ` [PATCH 1/4] dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts Kishon Vijay Abraham I @ 2021-03-25 9:09 ` Kishon Vijay Abraham I 2021-03-25 20:41 ` Bjorn Helgaas 2021-03-25 9:09 ` [PATCH 3/4] PCI: j721e: Add PCIe support for j7200 Kishon Vijay Abraham I 2021-03-25 9:09 ` [PATCH 4/4] PCI: j721e: Add PCIe support for AM64 Kishon Vijay Abraham I 3 siblings, 1 reply; 8+ messages in thread From: Kishon Vijay Abraham I @ 2021-03-25 9:09 UTC (permalink / raw) To: Kishon Vijay Abraham I, Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi, Marc Zyngier Cc: Tom Joseph, linux-omap, linux-pci, devicetree, linux-kernel, linux-arm-kernel, Lokesh Vutla Add PCI legacy interrupt support for J721E. J721E has a single HW interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD. The HW interrupt line connected to GIC is a pulse interrupt whereas the legacy interrupts by definition is level interrupt. In order to provide level interrupt functionality to edge interrupt line, PCIe in J721E has provided IRQ_EOI register. When the SW writes to IRQ_EOI register after handling the interrupt, the IP checks the state of legacy interrupt and re-triggers pulse interrupt invoking the handler again. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- drivers/pci/controller/cadence/pci-j721e.c | 91 ++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 0382bb15c6f9..17db86a51ca8 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -28,6 +28,13 @@ #define STATUS_CLR_REG_SYS_2 0x708 #define LINK_DOWN BIT(1) +#define EOI_REG 0x10 + +#define ENABLE_REG_SYS_0 0x100 +#define STATUS_REG_SYS_0 0x500 +#define STATUS_CLR_REG_SYS_0 0x700 +#define INTx_EN(num) (1 << (num)) + #define J721E_PCIE_USER_CMD_STATUS 0x4 #define LINK_TRAINING_ENABLE BIT(0) @@ -57,6 +64,7 @@ struct j721e_pcie { struct cdns_pcie *cdns_pcie; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; + struct irq_domain *legacy_irq_domain; }; enum j721e_pcie_mode { @@ -116,6 +124,85 @@ static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); } +static void j721e_pcie_legacy_irq_handler(struct irq_desc *desc) +{ + int i; + u32 reg; + int virq; + struct j721e_pcie *pcie = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + + chained_irq_enter(chip, desc); + + for (i = 0; i < PCI_NUM_INTX; i++) { + reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_0); + if (!(reg & INTx_EN(i))) + continue; + + virq = irq_find_mapping(pcie->legacy_irq_domain, 3 - i); + generic_handle_irq(virq); + j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_0, INTx_EN(i)); + j721e_pcie_intd_writel(pcie, EOI_REG, 3 - i); + } + + chained_irq_exit(chip, desc); +} + +static int j721e_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops j721e_pcie_intx_domain_ops = { + .map = j721e_pcie_intx_map, +}; + +static int j721e_pcie_config_legacy_irq(struct j721e_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct irq_domain *legacy_irq_domain; + struct device_node *node = dev->of_node; + struct device_node *intc_node; + int irq; + u32 reg; + int i; + + intc_node = of_get_child_by_name(node, "interrupt-controller"); + if (!intc_node) { + dev_WARN(dev, "legacy-interrupt-controller node is absent\n"); + return -EINVAL; + } + + irq = irq_of_parse_and_map(intc_node, 0); + if (!irq) { + dev_err(dev, "Failed to parse and map legacy irq\n"); + return -EINVAL; + } + irq_set_chained_handler_and_data(irq, j721e_pcie_legacy_irq_handler, + pcie); + + legacy_irq_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX, + &j721e_pcie_intx_domain_ops, + NULL); + if (!legacy_irq_domain) { + dev_err(dev, "Failed to add irq domain for legacy irqs\n"); + return -EINVAL; + } + pcie->legacy_irq_domain = legacy_irq_domain; + + for (i = 0; i < PCI_NUM_INTX; i++) { + reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_0); + reg |= INTx_EN(i); + j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_0, reg); + } + + return 0; +} + static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie) { struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev); @@ -385,6 +472,10 @@ static int j721e_pcie_probe(struct platform_device *pdev) goto err_get_sync; } + ret = j721e_pcie_config_legacy_irq(pcie); + if (ret < 0) + goto err_get_sync; + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); if (!bridge) { ret = -ENOMEM; -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/4] PCI: j721e: Add PCI legacy interrupt support for J721E 2021-03-25 9:09 ` [PATCH 2/4] PCI: j721e: Add PCI legacy interrupt support for J721E Kishon Vijay Abraham I @ 2021-03-25 20:41 ` Bjorn Helgaas 0 siblings, 0 replies; 8+ messages in thread From: Bjorn Helgaas @ 2021-03-25 20:41 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi, Marc Zyngier, Tom Joseph, linux-omap, linux-pci, devicetree, linux-kernel, linux-arm-kernel, Lokesh Vutla I'd promote J721E earlier in subject so it doesn't get truncated, e.g., PCI: j721e: Add J721E PCI legacy interrupt support On Thu, Mar 25, 2021 at 02:39:34PM +0530, Kishon Vijay Abraham I wrote: > +static void j721e_pcie_legacy_irq_handler(struct irq_desc *desc) > +{ > + int i; > + u32 reg; > + int virq; > + struct j721e_pcie *pcie = irq_desc_get_handler_data(desc); > + struct irq_chip *chip = irq_desc_get_chip(desc); The rest of this driver sorts locals in order of use, e.g., struct j721e_pcie *pcie = irq_desc_get_handler_data(desc); struct irq_chip *chip = irq_desc_get_chip(desc); int i; u32 reg; int virq; > + chained_irq_enter(chip, desc); > + > + for (i = 0; i < PCI_NUM_INTX; i++) { > + reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_0); > + if (!(reg & INTx_EN(i))) > + continue; > + > + virq = irq_find_mapping(pcie->legacy_irq_domain, 3 - i); Whitespace error (should be indented another tab, I think). > + generic_handle_irq(virq); > + j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_0, INTx_EN(i)); > + j721e_pcie_intd_writel(pcie, EOI_REG, 3 - i); > + } > + > + chained_irq_exit(chip, desc); > +} ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 3/4] PCI: j721e: Add PCIe support for j7200 2021-03-25 9:09 [PATCH 0/4] PCI: Add legacy interrupt support in pci-j721e Kishon Vijay Abraham I 2021-03-25 9:09 ` [PATCH 1/4] dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts Kishon Vijay Abraham I 2021-03-25 9:09 ` [PATCH 2/4] PCI: j721e: Add PCI legacy interrupt support for J721E Kishon Vijay Abraham I @ 2021-03-25 9:09 ` Kishon Vijay Abraham I 2021-04-02 11:17 ` Marc Zyngier 2021-03-25 9:09 ` [PATCH 4/4] PCI: j721e: Add PCIe support for AM64 Kishon Vijay Abraham I 3 siblings, 1 reply; 8+ messages in thread From: Kishon Vijay Abraham I @ 2021-03-25 9:09 UTC (permalink / raw) To: Kishon Vijay Abraham I, Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi, Marc Zyngier Cc: Tom Joseph, linux-omap, linux-pci, devicetree, linux-kernel, linux-arm-kernel, Lokesh Vutla J7200 has the same PCIe IP as in J721E with minor changes in the wrapper. Add PCIe support for j7200 accounting for the wrapper changes in pci-j721e.c Changes from J721E: *) Allows byte access of bridge configuration space registers *) Changes in legacy interrupt register map Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- drivers/pci/controller/cadence/pci-j721e.c | 111 ++++++++++++++++++--- 1 file changed, 99 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 17db86a51ca8..f175f116abf6 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -27,6 +27,7 @@ #define STATUS_REG_SYS_2 0x508 #define STATUS_CLR_REG_SYS_2 0x708 #define LINK_DOWN BIT(1) +#define J7200_LINK_DOWN BIT(10) #define EOI_REG 0x10 @@ -35,6 +36,10 @@ #define STATUS_CLR_REG_SYS_0 0x700 #define INTx_EN(num) (1 << (num)) +#define ENABLE_REG_SYS_1 0x104 +#define STATUS_REG_SYS_1 0x504 +#define SYS1_INTx_EN(num) (1 << (22 + (num))) + #define J721E_PCIE_USER_CMD_STATUS 0x4 #define LINK_TRAINING_ENABLE BIT(0) @@ -48,6 +53,14 @@ enum link_status { LINK_UP_DL_COMPLETED, }; +#define USER_EOI_REG 0xC8 +enum eoi_reg { + EOI_DOWNSTREAM_INTERRUPT, + EOI_FLR_INTERRUPT, + EOI_LEGACY_INTERRUPT, + EOI_POWER_STATE_INTERRUPT, +}; + #define J721E_MODE_RC BIT(7) #define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) @@ -65,6 +78,8 @@ struct j721e_pcie { void __iomem *user_cfg_base; void __iomem *intd_cfg_base; struct irq_domain *legacy_irq_domain; + bool is_intc_v1; + u32 link_irq_reg_field; }; enum j721e_pcie_mode { @@ -75,6 +90,9 @@ enum j721e_pcie_mode { struct j721e_pcie_data { enum j721e_pcie_mode mode; bool quirk_retrain_flag; + bool is_intc_v1; + bool byte_access_allowed; + const struct cdns_pcie_ops *ops; }; static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) @@ -106,12 +124,12 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) u32 reg; reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); - if (!(reg & LINK_DOWN)) + if (!(reg & pcie->link_irq_reg_field)) return IRQ_NONE; dev_err(dev, "LINK DOWN!\n"); - j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, LINK_DOWN); + j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->link_irq_reg_field); return IRQ_HANDLED; } @@ -119,12 +137,40 @@ static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) { u32 reg; + pcie->link_irq_reg_field = J7200_LINK_DOWN; + if (pcie->is_intc_v1) + pcie->link_irq_reg_field = LINK_DOWN; + reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); - reg |= LINK_DOWN; + reg |= pcie->link_irq_reg_field; j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); } static void j721e_pcie_legacy_irq_handler(struct irq_desc *desc) +{ + struct j721e_pcie *pcie = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + int virq; + u32 reg; + int i; + + chained_irq_enter(chip, desc); + + for (i = 0; i < PCI_NUM_INTX; i++) { + reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_1); + if (!(reg & SYS1_INTx_EN(i))) + continue; + + virq = irq_find_mapping(pcie->legacy_irq_domain, i); + generic_handle_irq(virq); + j721e_pcie_user_writel(pcie, USER_EOI_REG, + EOI_LEGACY_INTERRUPT); + } + + chained_irq_exit(chip, desc); +} + +static void j721e_pcie_v1_legacy_irq_handler(struct irq_desc *desc) { int i; u32 reg; @@ -182,8 +228,14 @@ static int j721e_pcie_config_legacy_irq(struct j721e_pcie *pcie) dev_err(dev, "Failed to parse and map legacy irq\n"); return -EINVAL; } - irq_set_chained_handler_and_data(irq, j721e_pcie_legacy_irq_handler, - pcie); + + if (pcie->is_intc_v1) { + irq_set_chained_handler_and_data(irq, j721e_pcie_v1_legacy_irq_handler, + pcie); + } else { + irq_set_chained_handler_and_data(irq, j721e_pcie_legacy_irq_handler, + pcie); + } legacy_irq_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX, &j721e_pcie_intx_domain_ops, @@ -194,10 +246,18 @@ static int j721e_pcie_config_legacy_irq(struct j721e_pcie *pcie) } pcie->legacy_irq_domain = legacy_irq_domain; - for (i = 0; i < PCI_NUM_INTX; i++) { - reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_0); - reg |= INTx_EN(i); - j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_0, reg); + if (pcie->is_intc_v1) { + for (i = 0; i < PCI_NUM_INTX; i++) { + reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_0); + reg |= INTx_EN(i); + j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_0, reg); + } + } else { + for (i = 0; i < PCI_NUM_INTX; i++) { + reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_1); + reg |= SYS1_INTx_EN(i); + j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_1, reg); + } } return 0; @@ -244,6 +304,12 @@ static const struct cdns_pcie_ops j721e_pcie_ops = { .link_up = j721e_pcie_link_up, }; +static const struct cdns_pcie_ops j7200_pcie_ops = { + .start_link = j721e_pcie_start_link, + .stop_link = j721e_pcie_stop_link, + .link_up = j721e_pcie_link_up, +}; + static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon, unsigned int offset) { @@ -371,10 +437,21 @@ static struct pci_ops cdns_ti_pcie_host_ops = { static const struct j721e_pcie_data j721e_pcie_rc_data = { .mode = PCI_MODE_RC, .quirk_retrain_flag = true, + .is_intc_v1 = true, + .byte_access_allowed = false, + .ops = &j721e_pcie_ops, }; static const struct j721e_pcie_data j721e_pcie_ep_data = { .mode = PCI_MODE_EP, + .ops = &j721e_pcie_ops, +}; + +static const struct j721e_pcie_data j7200_pcie_rc_data = { + .mode = PCI_MODE_RC, + .is_intc_v1 = false, + .byte_access_allowed = true, + .ops = &j7200_pcie_ops, }; static const struct of_device_id of_j721e_pcie_match[] = { @@ -386,6 +463,10 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,j721e-pcie-ep", .data = &j721e_pcie_ep_data, }, + { + .compatible = "ti,j7200-pcie-host", + .data = &j7200_pcie_rc_data, + }, {}, }; @@ -393,9 +474,11 @@ static int j721e_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *node = dev->of_node; + const struct cdns_pcie_ops *ops; struct pci_host_bridge *bridge; struct j721e_pcie_data *data; struct cdns_pcie *cdns_pcie; + bool byte_access_allowed; struct j721e_pcie *pcie; struct cdns_pcie_rc *rc; struct cdns_pcie_ep *ep; @@ -412,6 +495,8 @@ static int j721e_pcie_probe(struct platform_device *pdev) return -EINVAL; mode = (u32)data->mode; + byte_access_allowed = data->byte_access_allowed; + ops = data->ops; pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); if (!pcie) @@ -419,6 +504,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) pcie->dev = dev; pcie->mode = mode; + pcie->is_intc_v1 = data->is_intc_v1; base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg"); if (IS_ERR(base)) @@ -482,13 +568,14 @@ static int j721e_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - bridge->ops = &cdns_ti_pcie_host_ops; + if (!byte_access_allowed) + bridge->ops = &cdns_ti_pcie_host_ops; rc = pci_host_bridge_priv(bridge); rc->quirk_retrain_flag = data->quirk_retrain_flag; cdns_pcie = &rc->pcie; cdns_pcie->dev = dev; - cdns_pcie->ops = &j721e_pcie_ops; + cdns_pcie->ops = ops; pcie->cdns_pcie = cdns_pcie; gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); @@ -552,7 +639,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) cdns_pcie = &ep->pcie; cdns_pcie->dev = dev; - cdns_pcie->ops = &j721e_pcie_ops; + cdns_pcie->ops = ops; pcie->cdns_pcie = cdns_pcie; ret = cdns_pcie_init_phy(dev, cdns_pcie); -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 3/4] PCI: j721e: Add PCIe support for j7200 2021-03-25 9:09 ` [PATCH 3/4] PCI: j721e: Add PCIe support for j7200 Kishon Vijay Abraham I @ 2021-04-02 11:17 ` Marc Zyngier 0 siblings, 0 replies; 8+ messages in thread From: Marc Zyngier @ 2021-04-02 11:17 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi, Tom Joseph, linux-omap, linux-pci, devicetree, linux-kernel, linux-arm-kernel, Lokesh Vutla On Thu, 25 Mar 2021 09:09:35 +0000, Kishon Vijay Abraham I <kishon@ti.com> wrote: > > J7200 has the same PCIe IP as in J721E with minor changes in the > wrapper. Add PCIe support for j7200 accounting for the wrapper > changes in pci-j721e.c > Changes from J721E: > *) Allows byte access of bridge configuration space registers > *) Changes in legacy interrupt register map > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > drivers/pci/controller/cadence/pci-j721e.c | 111 ++++++++++++++++++--- > 1 file changed, 99 insertions(+), 12 deletions(-) > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c > index 17db86a51ca8..f175f116abf6 100644 > --- a/drivers/pci/controller/cadence/pci-j721e.c > +++ b/drivers/pci/controller/cadence/pci-j721e.c > @@ -27,6 +27,7 @@ > #define STATUS_REG_SYS_2 0x508 > #define STATUS_CLR_REG_SYS_2 0x708 > #define LINK_DOWN BIT(1) > +#define J7200_LINK_DOWN BIT(10) > > #define EOI_REG 0x10 > > @@ -35,6 +36,10 @@ > #define STATUS_CLR_REG_SYS_0 0x700 > #define INTx_EN(num) (1 << (num)) > > +#define ENABLE_REG_SYS_1 0x104 > +#define STATUS_REG_SYS_1 0x504 > +#define SYS1_INTx_EN(num) (1 << (22 + (num))) > + > #define J721E_PCIE_USER_CMD_STATUS 0x4 > #define LINK_TRAINING_ENABLE BIT(0) > > @@ -48,6 +53,14 @@ enum link_status { > LINK_UP_DL_COMPLETED, > }; > > +#define USER_EOI_REG 0xC8 > +enum eoi_reg { > + EOI_DOWNSTREAM_INTERRUPT, > + EOI_FLR_INTERRUPT, > + EOI_LEGACY_INTERRUPT, > + EOI_POWER_STATE_INTERRUPT, > +}; > + > #define J721E_MODE_RC BIT(7) > #define LANE_COUNT_MASK BIT(8) > #define LANE_COUNT(n) ((n) << 8) > @@ -65,6 +78,8 @@ struct j721e_pcie { > void __iomem *user_cfg_base; > void __iomem *intd_cfg_base; > struct irq_domain *legacy_irq_domain; > + bool is_intc_v1; > + u32 link_irq_reg_field; > }; > > enum j721e_pcie_mode { > @@ -75,6 +90,9 @@ enum j721e_pcie_mode { > struct j721e_pcie_data { > enum j721e_pcie_mode mode; > bool quirk_retrain_flag; > + bool is_intc_v1; > + bool byte_access_allowed; > + const struct cdns_pcie_ops *ops; > }; > > static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) > @@ -106,12 +124,12 @@ static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv) > u32 reg; > > reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2); > - if (!(reg & LINK_DOWN)) > + if (!(reg & pcie->link_irq_reg_field)) > return IRQ_NONE; > > dev_err(dev, "LINK DOWN!\n"); > > - j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, LINK_DOWN); > + j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->link_irq_reg_field); > return IRQ_HANDLED; > } > > @@ -119,12 +137,40 @@ static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie) > { > u32 reg; > > + pcie->link_irq_reg_field = J7200_LINK_DOWN; > + if (pcie->is_intc_v1) > + pcie->link_irq_reg_field = LINK_DOWN; > + > reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2); > - reg |= LINK_DOWN; > + reg |= pcie->link_irq_reg_field; > j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg); > } > > static void j721e_pcie_legacy_irq_handler(struct irq_desc *desc) > +{ > + struct j721e_pcie *pcie = irq_desc_get_handler_data(desc); > + struct irq_chip *chip = irq_desc_get_chip(desc); > + int virq; > + u32 reg; > + int i; > + > + chained_irq_enter(chip, desc); > + > + for (i = 0; i < PCI_NUM_INTX; i++) { > + reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_1); > + if (!(reg & SYS1_INTx_EN(i))) > + continue; > + > + virq = irq_find_mapping(pcie->legacy_irq_domain, i); > + generic_handle_irq(virq); > + j721e_pcie_user_writel(pcie, USER_EOI_REG, > + EOI_LEGACY_INTERRUPT); Exact same comment as in the previous patch: this EOI (which I assume is used to regenerate the GIC edge at after handling the INTx level interrupt) must be placed in a irq_eoi() callback. Thanks, M. -- Without deviation from the norm, progress is not possible. ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 4/4] PCI: j721e: Add PCIe support for AM64 2021-03-25 9:09 [PATCH 0/4] PCI: Add legacy interrupt support in pci-j721e Kishon Vijay Abraham I ` (2 preceding siblings ...) 2021-03-25 9:09 ` [PATCH 3/4] PCI: j721e: Add PCIe support for j7200 Kishon Vijay Abraham I @ 2021-03-25 9:09 ` Kishon Vijay Abraham I 3 siblings, 0 replies; 8+ messages in thread From: Kishon Vijay Abraham I @ 2021-03-25 9:09 UTC (permalink / raw) To: Kishon Vijay Abraham I, Bjorn Helgaas, Rob Herring, Lorenzo Pieralisi, Marc Zyngier Cc: Tom Joseph, linux-omap, linux-pci, devicetree, linux-kernel, linux-arm-kernel, Lokesh Vutla AM64 has the same PCIe IP as in J7200 (legacy interrupt handling is same as J7200 instead of J721E). Add support for "ti,am64-pcie-host" compatible that is specific to AM64. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- drivers/pci/controller/cadence/pci-j721e.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index f175f116abf6..38895a5f4b68 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -467,6 +467,10 @@ static const struct of_device_id of_j721e_pcie_match[] = { .compatible = "ti,j7200-pcie-host", .data = &j7200_pcie_rc_data, }, + { + .compatible = "ti,am64-pcie-host", + .data = &j7200_pcie_rc_data, + }, {}, }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2021-04-02 11:17 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-25 9:09 [PATCH 0/4] PCI: Add legacy interrupt support in pci-j721e Kishon Vijay Abraham I 2021-03-25 9:09 ` [PATCH 1/4] dt-bindings: PCI: ti,j721e: Add bindings to specify legacy interrupts Kishon Vijay Abraham I 2021-03-25 16:56 ` [PATCH 1/4] dt-bindings: PCI: ti, j721e: " Rob Herring 2021-03-25 9:09 ` [PATCH 2/4] PCI: j721e: Add PCI legacy interrupt support for J721E Kishon Vijay Abraham I 2021-03-25 20:41 ` Bjorn Helgaas 2021-03-25 9:09 ` [PATCH 3/4] PCI: j721e: Add PCIe support for j7200 Kishon Vijay Abraham I 2021-04-02 11:17 ` Marc Zyngier 2021-03-25 9:09 ` [PATCH 4/4] PCI: j721e: Add PCIe support for AM64 Kishon Vijay Abraham I
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