From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6B53C433ED for ; Sun, 16 May 2021 13:56:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9521C6113E for ; Sun, 16 May 2021 13:56:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233993AbhEPN54 (ORCPT ); Sun, 16 May 2021 09:57:56 -0400 Received: from smtp-35.italiaonline.it ([213.209.10.35]:42616 "EHLO libero.it" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S233870AbhEPN5z (ORCPT ); Sun, 16 May 2021 09:57:55 -0400 Received: from passgat-Modern-14-A10M.homenet.telecomitalia.it ([95.244.94.151]) by smtp-35.iol.local with ESMTPA id iHEzl2tgYpK9wiHF6lOWlZ; Sun, 16 May 2021 15:55:41 +0200 x-libjamoibt: 1601 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=libero.it; s=s2021; t=1621173341; bh=zZLQBLl9wixM7xxtZD+7yOPbluTczTOuH82A39eRwh8=; h=From; b=YW5enN5amP39PC+aP1tW2smXXvsDSBoFeX5O+8IL2EoEi6ZbB15HvlLptBx575g5K irlACxdTpZYmGCeEWUtpDAn+JAuqHfTrmMehRROecnTpHUdmFnpuxw4pC0RMSH/grP 1TZq8Fnxj/sQAHcugz/ADZCcBirg7Qg4vbzreYLr5MduhD/kmzca4/z4Ed3kMIXCB1 RPiRnweLLJtPdkkZvqEZvbdbdpH37m/qiqSkJU3NaEndxL8kogoVxVGTsp34SyHivF H8+JogyONt2mqkYfEZJGMwrYoW3cNaUwtLj0iT2jU11KnUFXRiJqcCO3qqXwCZgyRW s7jCQcRbxppuw== X-CNFS-Analysis: v=2.4 cv=A9ipg4aG c=1 sm=1 tr=0 ts=60a1245d cx=a_exe a=ugxisoNCKEotYwafST++Mw==:117 a=ugxisoNCKEotYwafST++Mw==:17 a=sozttTNsAAAA:8 a=hlofsd_XEJyvNm5uEDwA:9 a=aeg5Gbbo78KNqacMgKqU:22 From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Dario Binacchi , Haojian Zhuang , Linus Walleij , Tony Lindgren , linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH 2/2] pinctrl: single: set pinmux from pins debug file Date: Sun, 16 May 2021 15:55:31 +0200 Message-Id: <20210516135531.2203-3-dariobin@libero.it> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210516135531.2203-1-dariobin@libero.it> References: <20210516135531.2203-1-dariobin@libero.it> X-CMAE-Envelope: MS4xfJitAJ0M4XIXYHKFsdVSSJT/tz+2fn1XZyqRVv7cNGLeIY1LDkdsgw1cB9KctyKn3zYTLQ3J2o9S3lpE23G/fdUnSu6oIzDYCconWScoLDRvewSB93jK +adOMGnuKAiZD1fbVuhdaCd7yGWve3r5v4if3aGJvw+HFikj9rRLvD5sGm+rZARsa3bBpCMbA089B99Bz1mQUVg9kRajMStiHcVfG4eZE/TMiHlhqclh3G82 OUaKF7qKSMSefEDISPS8cxucIndJC5exNSBZb+oSw7T1+HWTON6GY3va5Ki4871D5wtW3QLD8nmcWV1tAQ6wfa+IwX6khJ/mwbtYXd3dxzJRyhtvHxlqpNoA 6WMWOlyXZRUMw1Z5/BHpmf6eswgdvVM1vCOTSfYKe8EerB1tnI1nKBo4EXt92QunELD2IHMdHdyOeI2Dm+QdOasSN+sXKyRm3f2Lf8F4/VkAyW5kLsF8SqY4 BzES+3DmXSMrLGbOcym3p2W4CupnRGT8YBEsZA== Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org As described in section 9.1 of the TI reference manual for AM335x [1], "For writing to the control module registers, the MPU will need to be in privileged mode of operation and writes will not work from user mode". By adding the pin_dbg_set helper to pcs_pinctrl_ops it will be possible to write these registers from the pins debug: cd /sys/kernel/debug/pinctrl/44e10800.pinmux-pinctrl-single/ echo

>pins [1] https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf Signed-off-by: Dario Binacchi --- drivers/pinctrl/pinctrl-single.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 2c9c9835f375..cdbc2298360d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -313,6 +313,23 @@ static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME); } +static int pcs_pin_dbg_set(struct pinctrl_dev *pctldev, unsigned int pin, + char *buf) +{ + struct pcs_device *pcs; + unsigned int val, mux_bytes; + + buf = skip_spaces(buf); + if (kstrtouint(buf, 0, &val)) + return -EINVAL; + + pcs = pinctrl_dev_get_drvdata(pctldev); + + mux_bytes = pcs->width / BITS_PER_BYTE; + pcs->write(val, pcs->base + pin * mux_bytes); + return 0; +} + static void pcs_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps) { @@ -331,6 +348,9 @@ static const struct pinctrl_ops pcs_pinctrl_ops = { .get_group_name = pinctrl_generic_get_group_name, .get_group_pins = pinctrl_generic_get_group_pins, .pin_dbg_show = pcs_pin_dbg_show, +#if IS_ENABLED(CONFIG_DEVMEM) && IS_ENABLED(CONFIG_SOC_AM33XX) + .pin_dbg_set = pcs_pin_dbg_set, +#endif .dt_node_to_map = pcs_dt_node_to_map, .dt_free_map = pcs_dt_free_map, }; -- 2.17.1