From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="JjIN6bUj" Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BCE8C129; Mon, 4 Dec 2023 10:23:45 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3B4IMqm7073793; Mon, 4 Dec 2023 12:22:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1701714172; bh=rD4bivD5C51EnE3KF9h6/z4d298ojSSuekhNSL43VNI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=JjIN6bUjyGz8ba5M87aF5pYD7oabto4+Uffkom5SgiEP1Msaete0s9woDYVrmw6BF BK8jXKarxYKhlo7Ips3WX081tBioV1de64+/XS4IyPoZUG3L3csaSVbdwIf3MJbdZZ rxYC1NCDRrbshosI9q7YQ6jtXn5nM0ukLgD07h+c= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3B4IMq5F091829 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 4 Dec 2023 12:22:52 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 4 Dec 2023 12:22:52 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 4 Dec 2023 12:22:52 -0600 Received: from fllv0039.itg.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3B4IMkx7042313; Mon, 4 Dec 2023 12:22:51 -0600 From: Andrew Davis To: Frank Binns , Donald Robson , Matt Coster , "H . Nikolaus Schaller" , Adam Ford , Ivaylo Dimitrov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?UTF-8?q?Beno=C3=AEt=20Cousson?= , Tony Lindgren , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Paul Cercueil CC: , , , , , , , Andrew Davis Subject: [PATCH RFC 04/10] ARM: dts: omap5: Add device tree entry for SGX GPU Date: Mon, 4 Dec 2023 12:22:39 -0600 Message-ID: <20231204182245.33683-5-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231204182245.33683-1-afd@ti.com> References: <20231204182245.33683-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-omap@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Add SGX GPU device entry to base OMAP5 dtsi file. Signed-off-by: Andrew Davis --- arch/arm/boot/dts/ti/omap/omap5.dtsi | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/ti/omap/omap5.dtsi b/arch/arm/boot/dts/ti/omap/omap5.dtsi index bac6fa8387936..6a66214ad0e2f 100644 --- a/arch/arm/boot/dts/ti/omap/omap5.dtsi +++ b/arch/arm/boot/dts/ti/omap/omap5.dtsi @@ -453,10 +453,11 @@ target-module@56000000 { #size-cells = <1>; ranges = <0 0x56000000 0x2000000>; - /* - * Closed source PowerVR driver, no child device - * binding or driver in mainline - */ + gpu@0 { + compatible = "ti,omap5432-gpu", "img,powervr-sgx544"; + reg = <0x0 0x2000000>; /* 32MB */ + interrupts = ; + }; }; target-module@58000000 { -- 2.39.2