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From: Dario Binacchi <dariobin@libero.it>
To: Tero Kristo <kristo@kernel.org>, linux-kernel@vger.kernel.org
Cc: Grygorii Strashko <grygorii.strashko@ti.com>,
	Lee Jones <lee.jones@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	linux-clk@vger.kernel.org, linux-omap@vger.kernel.org
Subject: Re: [PATCH v4 5/5] clk: ti: add am33xx/am43xx spread spectrum clock support
Date: Sun, 18 Apr 2021 16:50:03 +0200 (CEST)
Message-ID: <2042188966.804761.1618757403843@mail1.libero.it> (raw)
In-Reply-To: <b88d012a-b74c-6bd6-7465-3391921c9092@kernel.org>

Hi Tero,

> Il 16/04/2021 14:43 Tero Kristo <kristo@kernel.org> ha scritto:
> 
>  
> Hi Dario,
> 
> Spent some time looking at this, had to read through the TRM chapter of 
> it also in quite detailed level to figure out how this is supposed to 
> work out.
> 
> Other than couple of minor nits below, the code seems ok to me. What is 
> the testing that has been done with this?

The patch has been tested with laboratory instrumentation and is currently 
used on a custom board based on a AM335x SOC with a TI 4.1.6 kernel. It was born 
from the need to reduce the electromagnetic emissions of the display to pass the
EMI certifications. The current patch is a port of that to the mainline kernel. 
The corrections to be made were minimal and not significant. I'm testing it on a 
beaglebone black board, verifying with devmem that the DPLL registers are correctly 
set.

> 
> On 01/04/2021 22:37, Dario Binacchi wrote:
> > The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs.
> > As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for
> > the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for
> > DDR, PER, and CORE PLLs.
> > 
> > Calculating the required values and setting the registers accordingly
> > was taken from the set_mpu_spreadspectrum routine contained in the
> > arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project.
> > 
> > In locked condition, DPLL output clock = CLKINP *[M/N]. In case of
> > SSC enabled, the reference manual explains that there is a restriction
> > of range of M values. Since the omap2_dpll_round_rate routine attempts
> > to select the minimum possible N, the value of M obtained is not
> > guaranteed to be within the range required. With the new "ti,min-div"
> > parameter it is possible to increase N and consequently M to satisfy the
> > constraint imposed by SSC.
> > 
> > Signed-off-by: Dario Binacchi <dariobin@libero.it>
> > 
> > ---
> 
> <snip>
> 
> >   	/* REVISIT: Set ramp-up delay? */
> > diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
> > index c62f6fa6763d..cba093de62d8 100644
> > --- a/include/linux/clk/ti.h
> > +++ b/include/linux/clk/ti.h
> > @@ -63,6 +63,18 @@ struct clk_omap_reg {
> >    * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
> >    * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
> >    * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
> > + * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
> > + * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
> > + * @ssc_modfreq_mant_mask: mask of the mantissa component in @ssc_modfreq_reg
> > + * @ssc_modfreq_exp_mask: mask of the exponent component in @ssc_modfreq_reg
> > + * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
> > + * @ssc_ack_mask: mask of the DPLL SSC turned on/off bit in @control_reg
> > + * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
> > + *                       @control_reg
> > + * @ssc_modfreq: the DPLL SSC frequency modulation in kHz
> > + * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent)
> > + * @ssc_downspread: require the only low frequency spread of the DPLL in SSC
> > + *                   mode
> >    * @flags: DPLL type/features (see below)
> >    *
> >    * Possible values for @flags:
> > @@ -110,6 +122,18 @@ struct dpll_data {
> >   	u8			auto_recal_bit;
> >   	u8			recal_en_bit;
> >   	u8			recal_st_bit;
> > +	struct clk_omap_reg	ssc_deltam_reg;
> > +	struct clk_omap_reg	ssc_modfreq_reg;
> > +	u32			ssc_deltam_int_mask;
> > +	u32			ssc_deltam_frac_mask;
> > +	u32			ssc_modfreq_mant_mask;
> > +	u32			ssc_modfreq_exp_mask;
> > +	u32                     ssc_enable_mask;
> > +	u32                     ssc_ack_mask;
> 
> ssc_ack_mask is not used for anything in the code.

Ok, I will remove it.

> 
> > +	u32                     ssc_downspread_mask;
> > +	u32                     ssc_modfreq;
> > +	u32                     ssc_deltam;
> > +	u8                      ssc_downspread;
> 
> ssc_downspread should be boolean?

Yes.

Thanks and regards,
Dario

> 
> >   	u8			flags;
> >   };
> >   
> >

      reply index

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-01 19:37 [PATCH v4 0/5] clk: ti: add am33xx " Dario Binacchi
2021-04-01 19:37 ` [PATCH v4 1/5] clk: ti: fix typo in routine description Dario Binacchi
2021-04-01 19:37 ` [PATCH v4 3/5] ARM: dts: am33xx-clocks: add spread spectrum support Dario Binacchi
2021-04-01 19:37 ` [PATCH v4 4/5] ARM: dts: am43xx-clocks: " Dario Binacchi
2021-04-01 19:37 ` [PATCH v4 5/5] clk: ti: add am33xx/am43xx spread spectrum clock support Dario Binacchi
2021-04-16 12:43   ` Tero Kristo
2021-04-18 14:50     ` Dario Binacchi [this message]

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