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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Arnd Bergmann <arnd@arndb.de>, Tom Joseph <tjoseph@cadence.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	PCI <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	linux-omap <linux-omap@vger.kernel.org>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup
Date: Sat, 23 May 2020 06:54:18 +0530	[thread overview]
Message-ID: <44690fec-0b65-0192-75f7-e4fa086c4c0b@ti.com> (raw)
In-Reply-To: <CAL_Jsq+qcgKvauJ-GjsnmmpmRusyEJ6pRDpBOQKOadig4XfsxQ@mail.gmail.com>

Hi Rob,

On 5/22/2020 10:15 PM, Rob Herring wrote:
> On Thu, May 21, 2020 at 5:35 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>
>> Hi Rob,
>>
>> On 5/21/2020 3:04 AM, Rob Herring wrote:
>>> On Wed, May 06, 2020 at 08:44:22PM +0530, Kishon Vijay Abraham I wrote:
>>>> Cadence driver uses "mem" memory resource to obtain the offset of
>>>> configuration space address region, memory space address region and
>>>> message space address region. The obtained offset is used to program
>>>> the Address Translation Unit (ATU). However certain platforms like TI's
>>>> J721E SoC require the absolute address to be programmed in the ATU and not
>>>> just the offset.
>>>
>>> Once again, Cadence host binding is broken (or at least the example is).
>>> The 'mem' region shouldn't even exist. It is overlapping the config
>>> space and 'ranges':
>>>
>>>             reg = <0x0 0xfb000000  0x0 0x01000000>,
>>>                   <0x0 0x41000000  0x0 0x00001000>,
>>>                   <0x0 0x40000000  0x0 0x04000000>;
>>>             reg-names = "reg", "cfg", "mem";
>>>
>>>             ranges = <0x02000000 0x0 0x42000000  0x0 0x42000000  0x0 0x1000000>,
>>>                      <0x01000000 0x0 0x43000000  0x0 0x43000000  0x0 0x0010000>;
>>>
>>>
>>> 16M of registers looks a bit odd. I guess it doesn't matter
>>> unless you have a 32-bit platform and care about your virtual
>>> space. Probably should have been 3 regions for LM, RP, and AT looking
>>> at the driver.
>>
>> The "mem" region in never ioremapped. However $patch removes requiring to add
>> "mem" memory resource.
> 
> I was referring to ioremapping 'reg' region.
> 
>>>
>>> Whatever outbound address translation you need should be based on
>>> 'ranges'.
>>
>> You mean we don't need to add "new *ops* for CPU addr fixup"?. The issue is
>> ranges provides CPU address and PCI address. The CPU will access whatever is
>> populated in ranges to access the PCI bus. However while programming the ATU,
>> we cannot use the CPU address provided in ranges directly (in some platforms)
>> because the controller does not see the full address and only the lower 28bits.
> 
> Okay, that is clearer as to what the difference is. I think this
> should be 2 patches. One dropping 'mem' usage and using a mask and the
> 2nd making the mask per platform.

hmm okay.
> 
> Really, the parent node of the PCI controller should probably have
> 'ranges' and you could extract a mask from that. Looks like that is
> what you had for DRA7... I'm not sure if ABI stability is important
> for the Cadence platform. I'd assume that's just some IP eval system
> and probably not?

Right TI's J721E should be the first HW platform to use Cadence in mainline.
> 
> Why do you need an ops here? All you need is a mask value.

So how do we get platform specific mask? Use a different binding to specify the
mask value?
> 
>> This similar restriction was there with Designware (mostly an integration
>> issue) and we used *ops* to fixup the address that has to be programmed in ATU.
>> The Designware initially used a wrapper so that ranges property can be directly
>> used [1]. However this approach was later removed in [2]
>>
>> [1] -> https://lore.kernel.org/patchwork/patch/468523/
>> [2] -> https://lkml.org/lkml/2015/10/16/232
> 
> So while you had the data for a mask in DT, the driver now hardcodes it?

Yes, that's correct. Which approach should we use for Cadence?

Thanks
Kishon

  reply	other threads:[~2020-05-23  1:24 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-06 15:14 [PATCH v4 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 01/14] PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path Kishon Vijay Abraham I
2020-05-20 20:59   ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 02/14] linux/kernel.h: Add PTR_ALIGN_DOWN macro Kishon Vijay Abraham I
2020-05-20 21:00   ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 03/14] PCI: cadence: Add support to use custom read and write accessors Kishon Vijay Abraham I
2020-05-20 21:02   ` Rob Herring
2020-05-20 22:07   ` Rob Herring
2020-05-21 13:33     ` Kishon Vijay Abraham I
2020-05-21 22:17       ` Rob Herring
2020-05-22  3:36         ` Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 04/14] PCI: cadence: Add support to start link and verify link status Kishon Vijay Abraham I
2020-05-20 21:06   ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 05/14] PCI: cadence: Add read/write accessors to perform only 32-bit accesses Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 06/14] PCI: cadence: Allow pci_host_bridge to have custom pci_ops Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup Kishon Vijay Abraham I
2020-05-20 21:34   ` Rob Herring
2020-05-21 11:34     ` Kishon Vijay Abraham I
2020-05-22 16:45       ` Rob Herring
2020-05-23  1:24         ` Kishon Vijay Abraham I [this message]
2020-05-06 15:14 ` [PATCH v4 08/14] PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register Kishon Vijay Abraham I
2020-05-20 21:36   ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 09/14] PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 10/14] dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 11/14] dt-bindings: PCI: Add EP " Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 12/14] PCI: j721e: Add TI J721E PCIe driver Kishon Vijay Abraham I
2020-05-06 15:14 ` [PATCH v4 13/14] misc: pci_endpoint_test: Add J721E in pci_device_id table Kishon Vijay Abraham I
2020-05-20 22:12   ` Rob Herring
2020-05-06 15:14 ` [PATCH v4 14/14] MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe Kishon Vijay Abraham I
2020-05-20 22:12   ` Rob Herring
2020-05-18 11:14 ` [PATCH v4 00/14] Add PCIe support to TI's J721E SoC Kishon Vijay Abraham I

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