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([2a01:e34:ed2f:f020:2091:71d6:3ab2:37f2]) by smtp.googlemail.com with ESMTPSA id v18sm21863898wrf.41.2021.03.22.11.23.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Mar 2021 11:23:37 -0700 (PDT) Subject: Re: [PATCH 1/2] clocksource/drivers/timer-ti-dm: Prepare to handle dra7 timer wrap issue To: Tony Lindgren Cc: Thomas Gleixner , Keerthy , linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tero Kristo References: <20210304073737.15810-1-tony@atomide.com> <20210304073737.15810-2-tony@atomide.com> <556d55af-0b30-8751-6aef-2e1bb9db1a76@linaro.org> From: Daniel Lezcano Message-ID: <5c3c2447-3f8c-160c-8761-e43c1b4ebbf9@linaro.org> Date: Mon, 22 Mar 2021 19:23:36 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On 22/03/2021 17:33, Tony Lindgren wrote: > Hi, > > * Daniel Lezcano [210322 15:56]: >> On 04/03/2021 08:37, Tony Lindgren wrote: >>> There is a timer wrap issue on dra7 for the ARM architected timer. >>> In a typical clock configuration the timer fails to wrap after 388 days. >>> >>> To work around the issue, we need to use timer-ti-dm timers instead. >>> >>> Let's prepare for adding support for percpu timers by adding a common >>> dmtimer_clkevt_init_common() and call it from dmtimer_clockevent_init(). >>> This patch makes no intentional functional changes. >>> >>> Signed-off-by: Tony Lindgren >>> --- >> >> [ ... ] >> >>> @@ -575,33 +574,60 @@ static int __init dmtimer_clockevent_init(struct device_node *np) >>> */ >>> writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl); >>> >>> + if (dev->cpumask == cpu_possible_mask) >>> + irqflags = IRQF_TIMER; >>> + else >>> + irqflags = IRQF_TIMER | IRQF_NOBALANCING; >> >> Can you explain the reasoning behind the test above ? > > In the per cpu case we assign one dmtimer per cpu, and we want the > interrupt handling on the assigned CPU. In the per cpu case we have > the cpu specified with dev->cpumask unlike for the normal clockevent > case. > > In the per cpu dmtimer case the interrupt line is not wired per cpu > though, so I don't think we want to add IRQF_PERCPU here. If it is per cpu, then the parameter will be cpumask_of(cpu). If there is one cpu, no balancing can happen and then the IRQF_NOBALANCING is not needed, neither this test and the irqflags, right? -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog