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Sun, 8 Aug 2021 15:13:56 +0000 Received: from [10.25.99.72] (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 8 Aug 2021 15:13:45 +0000 Subject: Re: [PATCH v2 03/40] PCI: dwc: Allow overriding bridge pci_ops To: Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi CC: , Andy Gross , Binghui Wang , Bjorn Andersson , Dilip Kota , Fabio Estevam , Gustavo Pimentel , Jerome Brunet , Jesper Nilsson , Jingoo Han , Jonathan Chocron , Jonathan Hunter , Kevin Hilman , "Kishon Vijay Abraham I" , Krzysztof Kozlowski , Kukjin Kim , Kunihiko Hayashi , "Lucas Stach" , Martin Blumenstingl , Masahiro Yamada , Murali Karicheri , "Neil Armstrong" , NXP Linux Team , Pengutronix Kernel Team , Pratyush Anand , Richard Zhu , Sascha Hauer , Shawn Guo , Shawn Guo , Stanimir Varbanov , "Thierry Reding" , Xiaowei Song , Yue Wang , Marc Zyngier , , , , , , , References: <20200821035420.380495-1-robh@kernel.org> <20200821035420.380495-4-robh@kernel.org> From: Vidya Sagar Message-ID: <68e3adfb-a79d-3b70-87ed-2e5e1bf7fc93@nvidia.com> Date: Sun, 8 Aug 2021 20:43:43 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Aug 2021 15:13:56.1824 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d6bf1062-80fa-492d-644a-08d95a7f241e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.112.34];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5099 Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On 8/21/2020 9:23 AM, Rob Herring wrote: > In preparation to allow drivers to set their own root and child pci_ops > instead of using the DWC specific config space ops, we need to make > the pci_host_bridge pointer available and move setting the bridge->ops > and bridge->child_ops pointer to before the .host_init() hook. > > Cc: Jingoo Han > Cc: Gustavo Pimentel > Cc: Lorenzo Pieralisi > Cc: Bjorn Helgaas > Signed-off-by: Rob Herring > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 15 ++++++++++----- > drivers/pci/controller/dwc/pcie-designware.h | 1 + > 2 files changed, 11 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 1d98554db009..b626cc7cd43a 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -344,6 +344,8 @@ int dw_pcie_host_init(struct pcie_port *pp) > if (!bridge) > return -ENOMEM; > > + pp->bridge = bridge; > + > /* Get the I/O and memory ranges from DT */ > resource_list_for_each_entry(win, &bridge->windows) { > switch (resource_type(win->res)) { > @@ -445,6 +447,10 @@ int dw_pcie_host_init(struct pcie_port *pp) > } > } > > + /* Set default bus ops */ > + bridge->ops = &dw_pcie_ops; > + bridge->child_ops = &dw_pcie_ops; > + > if (pp->ops->host_init) { > ret = pp->ops->host_init(pp); > if (ret) > @@ -452,7 +458,6 @@ int dw_pcie_host_init(struct pcie_port *pp) > } > > bridge->sysdata = pp; > - bridge->ops = &dw_pcie_ops; > > ret = pci_scan_root_bus_bridge(bridge); > if (ret) > @@ -654,11 +659,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > dw_pcie_writel_dbi(pci, PCI_COMMAND, val); > > /* > - * If the platform provides ->rd_other_conf, it means the platform > - * uses its own address translation component rather than ATU, so > - * we should not program the ATU here. > + * If the platform provides its own child bus config accesses, it means > + * the platform uses its own address translation component rather than > + * ATU, so we should not program the ATU here. It is possible that a platform can have its own translation for configuration accesses and use DWC's ATU for memory/IO address translations. IMHO, ATU setup for memory/IO address translations shouldn't be skipped based on platform's '->rd_other_conf' implementation. Ex:- A platform can implement configuration space access through the ECAM mechanism yet choose to use ATU for memory/IO address translations. Thanks, Vidya Sagar > */ > - if (!pp->ops->rd_other_conf) { > + if (pp->bridge->child_ops == &dw_pcie_ops && !pp->ops->rd_other_conf) { > dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, > PCIE_ATU_TYPE_MEM, pp->mem_base, > pp->mem_bus_addr, pp->mem_size); > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index f911760dcc69..8b8ea5f3e7af 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -200,6 +200,7 @@ struct pcie_port { > u32 num_vectors; > u32 irq_mask[MAX_MSI_CTRLS]; > struct pci_bus *root_bus; > + struct pci_host_bridge *bridge; > raw_spinlock_t lock; > DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); > }; >