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([2a02:810d:340:2e50:10d8:ba05:5002:2dff]) by smtp.gmail.com with ESMTPSA id y10sm12138259wma.5.2020.04.26.12.37.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 26 Apr 2020 12:37:19 -0700 (PDT) Subject: Re: [PATCH v7 01/12] dt-bindings: add img,pvrsgx.yaml for Imagination GPUs To: "H. Nikolaus Schaller" , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , =?UTF-8?Q?Beno=c3=aet_Cousson?= , Tony Lindgren , Paul Cercueil , Ralf Baechle , Paul Burton , James Hogan , Kukjin Kim , Krzysztof Kozlowski , Maxime Ripard , Chen-Yu Tsai , Thomas Bogendoerfer Cc: Jonathan Bakker , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, openpvrsgx-devgroup@letux.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com, linux-mips@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org References: <3a451e360fed84bc40287678b4d6be13821cfbc0.1587760454.git.hns@goldelico.com> From: Philipp Rossak Message-ID: <9d9998cc-33bf-7d8f-658b-8d6218338135@gmail.com> Date: Sun, 26 Apr 2020 21:36:58 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <3a451e360fed84bc40287678b4d6be13821cfbc0.1587760454.git.hns@goldelico.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Hi Nikolaus, On 24.04.20 22:34, H. Nikolaus Schaller wrote: > The Imagination PVR/SGX GPU is part of several SoC from > multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, > Allwinner A83 and others. > > With this binding, we describe how the SGX processor is > interfaced to the SoC (registers and interrupt). > > The interface also consists of clocks, reset, power but > information from data sheets is vague and some SoC integrators > (TI) deciced to use a PRCM wrapper (ti,sysc) which does > all clock, reset and power-management through registers > outside of the sgx register block. > > Therefore all these properties are optional. > > Tested by make dt_binding_check > > Signed-off-by: H. Nikolaus Schaller > --- > .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++ > 1 file changed, 150 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > new file mode 100644 > index 000000000000..33a9c4c6e784 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Imagination PVR/SGX GPU > + > +maintainers: > + - H. Nikolaus Schaller > + > +description: |+ > + This binding describes the Imagination SGX5 series of 3D accelerators which > + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780, > + Allwinner A83, and Intel Poulsbo and CedarView and more. > + > + For an extensive list see: https://en.wikipedia.org/wiki/PowerVR#Implementations > + > + The SGX node is usually a child node of some DT node belonging to the SoC > + which handles clocks, reset and general address space mapping of the SGX > + register area. If not, an optional clock can be specified here. > + > +properties: > + $nodename: > + pattern: '^gpu@[a-f0-9]+$' > + compatible: > + oneOf: > + - description: SGX530-121 based SoC > + items: > + - enum: > + - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar > + - const: img,sgx530-121 > + - const: img,sgx530 > + > + - description: SGX530-125 based SoC > + items: > + - enum: > + - ti,am3352-sgx530-125 # BeagleBone Black > + - ti,am3517-sgx530-125 > + - ti,am4-sgx530-125 > + - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar > + - ti,ti81xx-sgx530-125 > + - const: ti,omap3-sgx530-125 > + - const: img,sgx530-125 > + - const: img,sgx530 > + > + - description: SGX535-116 based SoC > + items: > + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx > + - const: img,sgx535-116 > + - const: img,sgx535 > + > + - description: SGX540-116 based SoC > + items: > + - const: intel,medfield-gma-sgx540 # Atom Z24xx > + - const: img,sgx540-116 > + - const: img,sgx540 > + > + - description: SGX540-120 based SoC > + items: > + - enum: > + - samsung,s5pv210-sgx540-120 > + - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar > + - const: img,sgx540-120 > + - const: img,sgx540 > + > + - description: SGX540-130 based SoC > + items: > + - enum: > + - ingenic,jz4780-sgx540-130 # CI20 > + - const: img,sgx540-130 > + - const: img,sgx540 > + > + - description: SGX544-112 based SoC > + items: > + - const: ti,omap4470-sgx544-112 > + - const: img,sgx544-112 > + - const: img,sgx544 > + > + - description: SGX544-115 based SoC > + items: > + - enum: > + - allwinner,sun8i-a31-sgx544-115 > + - allwinner,sun8i-a31s-sgx544-115 those two bindings are wrong. It should be allwinner,sun6i-a31-sgx544-115 and allwinner,sun6i-a31s-sgx544-115. I did a copy paste error in the patches that I provided for this series. Cheers, Philipp