From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8268C56202 for ; Thu, 29 Oct 2020 13:02:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 574C720809 for ; Thu, 29 Oct 2020 13:02:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603976556; bh=OzIlRpXLdeGRcoA/MVFEQyHps4XuaG+UwlBrggFdE0A=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=iptXws0bUgMUpR02QXh0ow9ADrHyNMQDDC5OkiTpg95eeol4sMXWOzaFB+8dSIGuS /oXmqoX3PHHokgVkTqdw9ON5dLyWo/VKrgRXJY/XF9fjp3wSG23Q1ABI4sGg4y982Z yuBeJBVCxJgHycmYYC/RgFIgKkqX7PnjZQOH4HgQ= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725807AbgJ2NCe (ORCPT ); Thu, 29 Oct 2020 09:02:34 -0400 Received: from mail.kernel.org ([198.145.29.99]:33206 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725355AbgJ2NCd (ORCPT ); Thu, 29 Oct 2020 09:02:33 -0400 Received: from mail-ot1-f42.google.com (mail-ot1-f42.google.com [209.85.210.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 38CD321775; Thu, 29 Oct 2020 13:01:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1603976507; bh=OzIlRpXLdeGRcoA/MVFEQyHps4XuaG+UwlBrggFdE0A=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=j1mT2NYHsoJ27PjrIOdCHm29Dr0jIJanUSSvW3ovjtCA+2JsQwP4TF17V8h45KLn6 q/rWGnzjK5R5HCKtdT1UjO2CPNs0DlEyYrKGlf249zeQobn/tqoqqoSOkKF0nQ/tJx XzpLkOIXBR85Tjr1fxwi0eRNQozFeZBPxlNnWRvE= Received: by mail-ot1-f42.google.com with SMTP id 32so2168065otm.3; Thu, 29 Oct 2020 06:01:47 -0700 (PDT) X-Gm-Message-State: AOAM5329DpT5iisbFeMEkjPiTDZobOkh/2X8xi/6R5qq43OgNt+uDnFa blf46M/oSl5GRRIFDY/naVaedT2VoUIM2xChbQ== X-Google-Smtp-Source: ABdhPJy/bhS7KTF1WNqgQUUalxQA1GfpAd7FTQIi3yYFWyIBt0GxzCWPuCwRMAMfnaaUFyZdFb4NCZ8rTg453LUEqGQ= X-Received: by 2002:a9d:62d1:: with SMTP id z17mr3193317otk.192.1603976506229; Thu, 29 Oct 2020 06:01:46 -0700 (PDT) MIME-Version: 1.0 References: <20201028204646.356535-1-robh@kernel.org> <20201028204646.356535-2-robh@kernel.org> <87h7qdx4oz.fsf@mpe.ellerman.id.au> In-Reply-To: <87h7qdx4oz.fsf@mpe.ellerman.id.au> From: Rob Herring Date: Thu, 29 Oct 2020 08:01:35 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 01/13] PCI: dwc/imx6: Drop setting PCI_MSI_FLAGS_ENABLE To: Michael Ellerman Cc: Lorenzo Pieralisi , Kunihiko Hayashi , Neil Armstrong , PCI , Binghui Wang , Bjorn Andersson , linux-tegra , Thierry Reding , linux-arm-kernel@axis.com, Thomas Petazzoni , Jonathan Chocron , Shawn Guo , Jonathan Hunter , Fabio Estevam , Jerome Brunet , Jesper Nilsson , linux-samsung-soc , Minghuan Lian , Kevin Hilman , Pratyush Anand , Krzysztof Kozlowski , Kishon Vijay Abraham I , Kukjin Kim , NXP Linux Team , Xiaowei Song , Richard Zhu , Martin Blumenstingl , linux-arm-msm , Sascha Hauer , Yue Wang , Murali Karicheri , Bjorn Helgaas , "open list:ARM/Amlogic Meson..." , linux-omap , Mingkai Hu , Roy Zang , Masahiro Yamada , Jingoo Han , Andy Gross , Stanimir Varbanov , Pengutronix Kernel Team , Gustavo Pimentel , linuxppc-dev , Lucas Stach Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org On Wed, Oct 28, 2020 at 7:21 PM Michael Ellerman wrote: > > Rob Herring writes: > > No other host driver sets the PCI_MSI_FLAGS_ENABLE bit, so it must not > > be necessary. If it is, a comment is needed. > > Yeah, but git blame directly points to: > > 75cb8d20c112 ("PCI: imx: Enable MSI from downstream components") I think I did read this at some point and then forgot about it when I made the change later... > Which has a pretty long explanation. The relevant bit probably being: > > ... on i.MX6, the MSI Enable bit controls delivery of MSI interrupts > from components below the Root Port. The thing is that all seems not i.MX6 specific but DWC specific given MSI handling is contained within the DWC block. So I don't see how this could be an integration difference. So maybe everyone else is still just setting CONFIG_PCIEPORTBUS typically and haven't noticed? Is it correct for the host driver to set MSI enable? Rob