Re: [PATCH v4 3/5] irqchip/irq-pruss-intc: Add logic for handling reserved interrupts

From: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
To: Marc Zyngier <maz@kernel.org>
Cc: tglx@linutronix.de, jason@lakedaemon.net, "Anna,
	Suman" <s-anna@ti.com>,
	robh+dt@kernel.org, Lee Jones <lee.jones@linaro.org>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	david@lechnology.com, "Mills, William" <wmills@ti.com>,
	"Bajjuri, Praneeth" <praneeth@ti.com>
Subject: Re: [PATCH v4 3/5] irqchip/irq-pruss-intc: Add logic for handling reserved interrupts
Date: Wed, 29 Jul 2020 00:23:22 +0200	[thread overview]
Message-ID: <CAMxfBF7uaFMhGDTmVjZiAEiUxNFSBnh-qcEz3rSDhFTkWkrLkw@mail.gmail.com> (raw)
In-Reply-To: <1ae8b42d0e7a09caf01197b11cea2fff@kernel.org>

Hi Marc

On Tue, 28 Jul 2020 at 18:37, Marc Zyngier <maz@kernel.org> wrote:
>
> On 2020-07-28 10:18, Grzegorz Jaszczyk wrote:
> > From: Suman Anna <s-anna@ti.com>
> >
> > The PRUSS INTC has a fixed number of output interrupt lines that are
> > connected to a number of processors or other PRUSS instances or other
> > devices (like DMA) on the SoC. The output interrupt lines 2 through 9
> > are usually connected to the main Arm host processor and are referred
> > to as host interrupts 0 through 7 from ARM/MPU perspective.
> >
> > All of these 8 host interrupts are not always exclusively connected
> > to the Arm interrupt controller. Some SoCs have some interrupt lines
> > not connected to the Arm interrupt controller at all, while a few
> > others
> > have the interrupt lines connected to multiple processors in which they
> > need to be partitioned as per SoC integration needs. For example,
> > AM437x
> > and 66AK2G SoCs have 2 PRUSS instances each and have the host interrupt
> > 5
> > connected to the other PRUSS, while AM335x has host interrupt 0 shared
> > between MPU and TSC_ADC and host interrupts 6 & 7 shared between MPU
> > and
> > a DMA controller.
> >
> > Add logic to the PRUSS INTC driver to ignore both these shared and
> > invalid interrupts.
> >
> > Signed-off-by: Suman Anna <s-anna@ti.com>
> > Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
> > ---
> > v3->v4:
> > - Due to changes in DT bindings which converts irqs-reserved
> >   property from uint8-array to bitmask requested by Rob introduce
> >   relevant changes in the driver.
> > - Merge the irqs-reserved and irqs-shared to one property since they
> >   can be handled by one logic (relevant change was introduced to DT
> >   binding).
>
> This isn't what I asked for in my initial review.
>
> I repeatedly asked for the *handling* to be common, not for the
> properties to be merged. I don't mind either way, but I understood
> there were two properties for a good reason. Has this reason gone?

Yes, I am aware that you've asked for common handling. Nevertheless
due to this change the usage of irqs-shared had to change. Previously
Suman's intention was to always skip the irqs-reserved, while allowing
to try getting interrupts even from irqs-shared list but in case of
failure (during platform_get_irq_byname) it wasn't treated as an
error.
In other words: in the previous approach if the interrupt from
irqs-shared was present in DT interrupts property it was treated as a
valid resource. If the irqs-shared interrupt wasn't present in DT
interrupts property it was skipped (similar to the irqs-reserved
case).

Now after your request for handling both in a common way the
interpretation of irqs-shared had to change. Therefore there's no need
to have seperate property for them. Now it is simpler: if some
interrupt is present in irqs-reserved it will be skipped.

>
> Anyway, I'll come back to it once I start reviewing the series
> again.
>

Ok, thank you,
Grzegorz