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Thu, 2 Apr 2020 11:50:06 +0000 From: Peter Smith To: Ard Biesheuvel , Nick Desaulniers CC: Stefan Agner , Tony Lindgren , Russell King , LKML , clang-built-linux , "linux-omap@vger.kernel.org" , Linux ARM , nd Subject: Re: [PATCH] ARM: OMAP2+: drop unnecessary adrl Thread-Topic: [PATCH] ARM: OMAP2+: drop unnecessary adrl Thread-Index: AQHWCNPf3/UDtOa4QU2PsSz3b6wtIqhlszgI Date: Thu, 2 Apr 2020 11:50:06 +0000 Message-ID: References: <5a6807f19fd69f2de6622c794639cc5d70b9563a.1585513949.git.stefan@agner.ch> , In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Peter.Smith@arm.com; x-originating-ip: [217.140.106.52] x-ms-publictraffictype: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 1aebe411-bcce-41c3-1175-08d7d6fc01d4 x-ms-traffictypediagnostic: DBBPR08MB4235:|PR2PR08MB4651: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true nodisclaimer: true x-ms-oob-tlc-oobclassifiers: OLM:10000;OLM:10000; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4235 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Peter.Smith@arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT030.eop-EUR03.prod.protection.outlook.com X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFTY:;SFS:(10009020)(4636009)(39860400002)(136003)(376002)(396003)(346002)(46966005)(5660300002)(478600001)(86362001)(47076004)(110136005)(55016002)(33656002)(26005)(81156014)(82740400003)(70206006)(2906002)(54906003)(52536014)(26826003)(9686003)(186003)(6506007)(356004)(316002)(36906005)(336012)(7696005)(450100002)(8676002)(8936002)(4326008)(70586007)(81166006);DIR:OUT;SFP:1101; X-MS-Office365-Filtering-Correlation-Id-Prvs: 218812dc-5b3b-4cc6-4cf2-08d7d6fbfcf7 X-Forefront-PRVS: 0361212EA8 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: U0MxjAWKlYgHzuO7cleBwXcpbTomsNL1rmbuh3cyvh6lnM3KlrQ+L2Hz0gDVzbpvjFqpn1D1Ikm23vjPl/sBldfuAvUNRTitouRUxnuv8+cBk/VJTyHJdvv6ADvauVcWMb9OqXvOYJ1xrVyStULPb8IIM0lo9DPc7oGFGZ0Y4Q/aSJaYkegEXmyywVgIpNdpBTbxA9jB51GbDAfUCL0kdpWLZEtJTT/QYuW+RqeaMSzu6MPX+NlgXWrjdMosIpHK7BiecLRAFKFCya5feDa2HEgzZAfPEBz3getOPrHAiGoKSFjG5lWPPEoLJYqqqzZCqiB98wFDMc8VwMf5vla8enKdkoA3KDLYqPfMgG0eT+R1H9HN6vZU1MozpdJQDbE2JIwYaz9ZeORn8qeIbe5p2lQLT2xM4Nau2ACtcvAXHgtzByflYy0AUtMSbDTg1FGW916FFAYxBY60Pu5hMV1HAeo3cWei+C277a28xSbgy17S/tGuzNFWZqhpkM6f5GviLOMxLTSI4ZuVRo9tNNjXDw== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2020 11:50:14.6151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1aebe411-bcce-41c3-1175-08d7d6fc01d4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PR2PR08MB4651 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org > I take it this implies that the LLVM linker does not support the=0A= > R_ARM_ALU_PC_Gn relocations? Since otherwise, adrl could simply be=0A= > expanded to a pair of adds with the appropriate relocations, letting=0A= > the linker fix up the immediates (and the ADD vs SUB bits)=0A= =0A= Not at the moment. I have a patch in review to add the G0 variants for thes= e in Arm state at reviews.llvm.org/D75349 . As far as I know LLVM MC does n= ot have support for generating the relocations either. This could be added = though. I agree that using the G* relocations with a pair of add/sub instru= ctions would be the ideal solution. The adrl psuedo is essentially that but= implemented at assembly time. I think it would be possible to implement in= LLVM but at the time (4+ years ago) I wasn't confident in finding someone = that would think that adrl support was worth the disruption, for example th= e current Arm assembly backend can only produce 1 instruction as output and= adrl requires two.=0A= =0A= I'd be happy to look at group relocation support in LLD, I haven't got a lo= t of spare time so progress is likely to be slow though.=0A= =0A= Peter =