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Thu, 2 Apr 2020 17:50:04 +0000 From: Peter Smith To: Ard Biesheuvel CC: Nick Desaulniers , nd , Tony Lindgren , Russell King , Stefan Agner , LKML , clang-built-linux , "linux-omap@vger.kernel.org" , Linux ARM Subject: Re: [PATCH] ARM: OMAP2+: drop unnecessary adrl Thread-Topic: [PATCH] ARM: OMAP2+: drop unnecessary adrl Thread-Index: AQHWCNPf3/UDtOa4QU2PsSz3b6wtIqhlszgIgAAJCgCAAF834g== Date: Thu, 2 Apr 2020 17:50:04 +0000 Message-ID: References: <5a6807f19fd69f2de6622c794639cc5d70b9563a.1585513949.git.stefan@agner.ch> , In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-GB X-MS-Has-Attach: X-MS-TNEF-Correlator: Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Peter.Smith@arm.com; x-originating-ip: [217.140.106.52] x-ms-publictraffictype: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 8c659e06-3a25-4c46-32b1-08d7d72e4a5a x-ms-traffictypediagnostic: DBBPR08MB4839:|DB6PR0801MB1719: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true nodisclaimer: true x-ms-oob-tlc-oobclassifiers: OLM:10000;OLM:10000; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4839 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Peter.Smith@arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT007.eop-EUR03.prod.protection.outlook.com X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFTY:;SFS:(10009020)(4636009)(39860400002)(376002)(396003)(136003)(346002)(46966005)(26826003)(47076004)(478600001)(86362001)(966005)(70206006)(54906003)(107886003)(6506007)(82740400003)(186003)(70586007)(356004)(33656002)(8936002)(336012)(7696005)(450100002)(4326008)(2906002)(55016002)(52536014)(8676002)(6862004)(26005)(5660300002)(36906005)(9686003)(81166006)(81156014)(316002);DIR:OUT;SFP:1101; X-MS-Office365-Filtering-Correlation-Id-Prvs: eae70085-fa11-402a-e384-08d7d72e4652 X-Forefront-PRVS: 0361212EA8 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WVDUAkASdKzh6PJC2FV4hADAzPVUBurVIRGlilqO0srlWvHOpsVEcIQaViPikxU14CYkMhrx/IcyJAbfsh6K5F5qzjnwoJBS0gPQmMnGN+9i+1tsgcRYYG5fGE23yU02RWzSOfIPvlevihaIB+j1P2J2M7PmLAtIc4mZrK1S1fuZ07Net9XwRP61P1dzMz5cSq+4vAQYkjD93NFPCxhIAA/ydVMJtCEpk0qdK0h40PWYnQGj8+4sAvqtxB0Otw7MwWGscEX7eQ19q3Dw3e2Po86PRJwQ6pPCVg8xC75HPU6+5x+jJYE30I/KtefaIgnIa6hu4rbkrcVxXn/gx/Zpb9R3wXt3EiDoO4dEwIF9yxCqZUF4eppfnW0Ikh5aCRCDebHz4BehC1GDAzwDQMacZmJVvFPx8x7DvSDzHVW+XCPVDyEgz81ppr2UL2ZyDA/fMg6VZdnUaRSIUR7jLDcBynO9AY3RGsryf+FIg/oV8CtmGGupsp0fSyTL1BDNCQA03Bzq03yatjtlOu85H/zrZBaO0SUq9JK8UDQLqBZwKShR9lwwN2Eb2L+Bi6w2CY8bwIPKin/uAKwl7WFKIi/IFQ== X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2020 17:50:11.1316 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c659e06-3a25-4c46-32b1-08d7d72e4a5a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB6PR0801MB1719 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org =0A= =0A= =0A= =0A= > On Thu, 2 Apr 2020 at 13:50, Peter Smith wrote:=0A= > >=0A= > > > I take it this implies that the LLVM linker does not support the=0A= > > > R_ARM_ALU_PC_Gn relocations? Since otherwise, adrl could simply be=0A= > > > expanded to a pair of adds with the appropriate relocations, letting= =0A= > > > the linker fix up the immediates (and the ADD vs SUB bits)=0A= > >=0A= > > Not at the moment. I have a patch in review to add the G0 variants for = these in Arm state at reviews.llvm.org/D75349 . As far as I know LLVM MC do= es not have support for generating the relocations either. This could be ad= ded though. I agree that using the G* relocations with a pair of add/sub in= structions would be the ideal solution. The adrl psuedo is essentially that= but implemented at assembly time. I think it would be possible to implemen= t in LLVM but at the time (4+ years ago) I wasn't confident in finding some= one that would think that adrl support was worth the disruption, for exampl= e the current Arm assembly backend can only produce 1 instruction as output= and adrl requires two.=0A= > >=0A= > > I'd be happy to look at group relocation support in LLD, I haven't got = a lot of spare time so progress is likely to be slow though.=0A= > >=0A= =0A= > For Linux, I have proposed another approach in the past, which is to=0A= > define a (Linux-local) adr_l macro with unlimited range [0], which=0A= > basically comes down to place relative movw/movt pairs for v7+, and=0A= > something along the lines of=0A= =0A= > ldr , 222f=0A= > 111: add , , pc=0A= > .subsection 1=0A= > 222: .long - (111b + 8)=0A= > .previous=0A= >=0A= > for v6 and earlier. Could you comment on whether Clang's integrated=0A= > assembler could support anything like this?=0A= =0A= Apologies for the delay in responding.=0A= =0A= That looks like it should work. Empirically the following works in both Cla= ng and GNU as. One potential problem here is that if the section is large a= nd the subsections are dumped at the end the ldr is at risk of going out of= range.=0A= =0A= .arm=0A= .macro mylongadrl reg, sym=0A= ldr \reg, 222f=0A= 111: add \reg, \reg, pc=0A= .subsection 1=0A= 222: .long \sym - (111b + 8)=0A= .previous=0A= .endm =0A= =0A= .text=0A= foo: bx lr=0A= bar: bx lr=0A= mylongadrl r0 foo=0A= mylongadrl r0 bar=0A= =0A= > Thanks,=0A= > Ard.=0A= >=0A= >=0A= >=0A= > [0] https://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git/commit= /?h=3Darm-kaslr-latest&id=3Dfd440f1131553a5201ce3b94905419bd067b93b3=0A=