From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16D8AC433E1 for ; Wed, 27 May 2020 10:49:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EAF352075F for ; Wed, 27 May 2020 10:49:54 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="QWadH3xO" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729316AbgE0Ktv (ORCPT ); Wed, 27 May 2020 06:49:51 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54206 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726649AbgE0Ktv (ORCPT ); Wed, 27 May 2020 06:49:51 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04RAnZnC113309; Wed, 27 May 2020 05:49:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1590576575; bh=PD+boL1tjck4sdCDgLl/S8WZdUjIHY0I5B2iMdPDagU=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=QWadH3xOFV3pgUzj6qG4hBxcxtI/8N/9aKAye8xOuN2atXdd1fS2UpjsWwMsVoL+V xFmgJHBBGy11xtVTT7TaGZUKtvV0oXI7CctJ+U/7+S8RWjiTIBMKHpzaAa1aV3Srh/ dbKabKVR9yggVeExJmbzECP8fdGOUjsBZ6+wvMIk= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04RAnZKX073235; Wed, 27 May 2020 05:49:35 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 27 May 2020 05:49:35 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 27 May 2020 05:49:35 -0500 Received: from [10.250.233.85] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04RAnV0o056154; Wed, 27 May 2020 05:49:32 -0500 Subject: Re: [PATCH v5 03/14] PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses To: Rob Herring CC: Tom Joseph , Lorenzo Pieralisi , Bjorn Helgaas , PCI , "linux-kernel@vger.kernel.org" , Arnd Bergmann , Greg Kroah-Hartman , , linux-omap , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" References: <20200522033631.32574-1-kishon@ti.com> <20200522033631.32574-4-kishon@ti.com> From: Kishon Vijay Abraham I Message-ID: Date: Wed, 27 May 2020 16:19:31 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Hi Rob, On 5/26/2020 8:42 PM, Rob Herring wrote: > On Sun, May 24, 2020 at 9:30 PM Kishon Vijay Abraham I wrote: >> >> Hi Rob, >> >> On 5/22/2020 9:24 PM, Rob Herring wrote: >>> On Thu, May 21, 2020 at 9:37 PM Kishon Vijay Abraham I wrote: >>>> >>>> Certain platforms like TI's J721E using Cadence PCIe IP can perform only >>>> 32-bit accesses for reading or writing to Cadence registers. Convert all >>>> read and write accesses to 32-bit in Cadence PCIe driver in preparation >>>> for adding PCIe support in TI's J721E SoC. >>> >>> Looking more closely I don't think cdns_pcie_ep_assert_intx is okay >>> with this and never can be given the PCI_COMMAND and PCI_STATUS >>> registers are in the same word (IIRC, that's the main reason 32-bit >>> config space accesses are broken). So this isn't going to work at >> >> right, PCI_STATUS has write '1' to clear bits and there's a chance that it >> could be reset while raising legacy interrupt. While this cannot be avoided for >> TI's J721E, other platforms doesn't have to have this limitation. >>> least for EP accesses. And maybe you need a custom .raise_irq() hook >>> to minimize any problems (such as making the RMW atomic at least from >>> the endpoint's perspective). >> >> This is to make sure EP doesn't update in-consistent state when RC is updating >> the PCI_STATUS register? Since this involves two different systems, how do we >> make this atomic? > > You can't make it atomic WRT both systems, but is there locking around > each RMW? Specifically, are preemption and interrupts disabled to > ensure time between a read and write are minimized? You wouldn't want > interrupts disabled during the delay too though (i.e. around > .raise_irq()). Okay, I'll add spin spin_lock_irqsave() in cdns_pcie_write_sz(). As you also pointed below that delay for legacy interrupt is wrong and it has to be fixed (with a later series). How do you want to handle cdns_pcie_ep_fn_writew() now? Because now we are changing the default implementation to perform only 32-bit access (used for legacy interrupt, msi-x interrupt and while writing standard headers) and it's not okay only for legacy interrupts for platforms other than TI. So just for legacy interrupt, you want me to add a different accessor which does not perform 32-bit writes (while we add a different .raise_irq for TI platform? > > BTW, I've asked this question before, but aren't PCI legacy interrupts > level triggered? If so, isn't generating a pulse wrong? You are right. This is wrong and it has to be fixed. I'll work on this later. Thanks Kishon