From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.4 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBF65C10DCE for ; Thu, 12 Mar 2020 08:06:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B6F8920716 for ; Thu, 12 Mar 2020 08:06:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="tqC4zg2t" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726865AbgCLIG3 (ORCPT ); Thu, 12 Mar 2020 04:06:29 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:53744 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725268AbgCLIG3 (ORCPT ); Thu, 12 Mar 2020 04:06:29 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02C86KXG105763; Thu, 12 Mar 2020 03:06:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1584000380; bh=J5M0FMAC5tNLJClXhjgw9z/u+wvqtVNBtEKQ1U48aok=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=tqC4zg2twBtiPRZcL3GzBPAe1SxMSTj4g9Eei8p7WIXr76mpGiHued15tqXOf6EIS bXgzI7O2R7W/CAIS0bhiKN3Ff/Ac1OZLp4qJUYL1Fo3BtX+x6ckeRhtk+N9vzQYxD3 gK+yGHtCfHuE88LeAP8GjrVdT5Xeyvr94AlMgcqc= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02C86Kb9104433 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 12 Mar 2020 03:06:20 -0500 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 12 Mar 2020 03:06:20 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 12 Mar 2020 03:06:20 -0500 Received: from [10.24.69.20] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02C86Hlc020278; Thu, 12 Mar 2020 03:06:18 -0500 Subject: Re: [PATCH v3 4/5] pwm: omap-dmtimer: Do not disable pwm before changing period/duty_cycle To: =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= CC: Thierry Reding , Tony Lindgren , Linux OMAP Mailing List , , , Sekhar Nori , Vignesh R References: <20200312042210.17344-1-lokeshvutla@ti.com> <20200312042210.17344-5-lokeshvutla@ti.com> <20200312064042.p7himm3odxjyzroi@pengutronix.de> From: Lokesh Vutla Message-ID: Date: Thu, 12 Mar 2020 13:35:32 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <20200312064042.p7himm3odxjyzroi@pengutronix.de> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Hi Uwe, On 12/03/20 12:10 PM, Uwe Kleine-König wrote: > On Thu, Mar 12, 2020 at 09:52:09AM +0530, Lokesh Vutla wrote: >> Only the Timer control register(TCLR) cannot be updated when the timer >> is running. Registers like Counter register(TCRR), loader register(TLDR), >> match register(TMAR) can be updated when the counter is running. Since >> TCLR is not updated in pwm_omap_dmtimer_config(), do not stop the >> timer for period/duty_cycle update. > > I'm not sure what is sensible here. Stopping the PWM for a short period > is bad, but maybe emitting a wrong period isn't better. You can however > optimise it if only one of period or duty_cycle changes. > > @Thierry, what is your position here? I tend to say a short stop is > preferable. Short stop has side effects especially in the case where 1PPS is generated using this PWM. In this case where PWM period is continuously synced with PTP clock, cannot expect any breaks in PWM. This doesn't fall in the above limitations as well. as duty_cycle is not a worry and only the rising edge is all that matters. Also any specific reason why you wanted to stop rather than having the mentioned limitation? it is just a corner anyway and doesn't happen all the time. Thanks and regards, Lokesh > >> Tested-by: Tony Lindgren >> Signed-off-by: Lokesh Vutla >> --- >> drivers/pwm/pwm-omap-dmtimer.c | 21 +++++++-------------- >> 1 file changed, 7 insertions(+), 14 deletions(-) >> >> diff --git a/drivers/pwm/pwm-omap-dmtimer.c b/drivers/pwm/pwm-omap-dmtimer.c >> index 85b17b49980b..c56e7256e923 100644 >> --- a/drivers/pwm/pwm-omap-dmtimer.c >> +++ b/drivers/pwm/pwm-omap-dmtimer.c >> @@ -19,6 +19,13 @@ >> * Limitations: >> * - When PWM is stopped, timer counter gets stopped immediately. This >> * doesn't allow the current PWM period to complete and stops abruptly. >> + * - When PWM is running and changing both duty cycle and period, >> + * we cannot prevent in software that the output might produce >> + * a period with mixed settings. Especially when period/duty_cyle >> + * is updated while the pwm pin is high, current pwm period/duty_cycle >> + * can get updated as below based on the current timer counter: >> + * - period for current cycle = current_period + new period >> + * - duty_cycle for current period = current period + new duty_cycle. > > In case we stay with a short stop, adding something like: > > - The PWM has to be stopped for updates of both period and duty_cycle. > > Best regards > Uwe >