From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Zijlstra Subject: Re: [PATCH 1/4] treewide: remove unused address argument from pte_alloc functions (v2) Date: Wed, 24 Oct 2018 10:37:16 +0200 Message-ID: <20181024083716.GN3109@worktop.c.hoisthospitality.com> References: <20181013013200.206928-1-joel@joelfernandes.org> <20181013013200.206928-2-joel@joelfernandes.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Cc: linux-mips@linux-mips.org, Rich Felker , linux-ia64@vger.kernel.org, linux-sh@vger.kernel.org, Catalin Marinas , Dave Hansen , Will Deacon , Michal Hocko , linux-mm@kvack.org, lokeshgidra@google.com, sparclinux@vger.kernel.org, linux-riscv@lists.infradead.org, elfring@users.sourceforge.net, Jonas Bonn , kvmarm@lists.cs.columbia.edu, dancol@google.com, Yoshinori Sato , linux-xtensa@linux-xtensa.org, linux-hexagon@vger.kernel.org, Helge Deller , "maintainer:X86 ARCHITECTURE \(32-BIT AND 64-BIT\)" , hughd@google.com, "James E.J. Bottomley" , kasan-dev@googlegroups.com, anton.ivanov@kot-begemot.co.uk, Ingo Molnar , Geert Uytterhoeven Return-path: In-Reply-To: <20181013013200.206928-2-joel@joelfernandes.org> List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: linux-snps-arc-bounces+gla-linux-snps-arc=m.gmane.org@lists.infradead.org On Fri, Oct 12, 2018 at 06:31:57PM -0700, Joel Fernandes (Google) wrote: > This series speeds up mremap(2) syscall by copying page tables at the > PMD level even for non-THP systems. There is concern that the extra > 'address' argument that mremap passes to pte_alloc may do something > subtle architecture related in the future that may make the scheme not > work. Also we find that there is no point in passing the 'address' to > pte_alloc since its unused. So this patch therefore removes this > argument tree-wide resulting in a nice negative diff as well. Also > ensuring along the way that the enabled architectures do not do anything > funky with 'address' argument that goes unnoticed by the optimization. Did you happen to look at the history of where that address argument came from? -- just being curious here. ISTR something vague about architectures having different paging structure for different memory ranges.