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* [PATCH v2] parisc: Various spin lock optimizations
@ 2020-07-21 12:59 John David Anglin
  0 siblings, 0 replies; only message in thread
From: John David Anglin @ 2020-07-21 12:59 UTC (permalink / raw)
  To: linux-parisc; +Cc: Helge Deller, James Bottomley

V2 adjusts the barrier used in arch_spin_unlock().

While investigating the stall problem, I looked closely at our spin lock implementation and found
a number of minor issues.

Regarding arch_spin_is_locked(), I wasn't convinced that the barrier was correct, so I switched the
code to use READ_ONCE.

Regarding arch_spin_lock(), cpu_relax() slightly pessimizes the loop code generated by gcc.  The pointer
"a" is volatile, so we can just use continue.

Regarding arch_spin_lock_flags(), I went back to the old code which just toggles interrupts on and off
in the wait loop.  It's rather dangerous to allow the routine to set all the PSW flag bits and wierd
things happen if local_save_flags() is moved.

Regarding arch_spin_unlock(), we can use an ordered store to release the lock and eliminate the ldcw
barrier.

Finally regarding arch_spin_trylock(), I just shortened the C code.

Signed-off-by: Dave Anglin <dave.anglin@bell.net>
---

diff --git a/arch/parisc/include/asm/spinlock.h b/arch/parisc/include/asm/spinlock.h
index 70fecb8dc4e2..ad40b3a8e8e9 100644
--- a/arch/parisc/include/asm/spinlock.h
+++ b/arch/parisc/include/asm/spinlock.h
@@ -10,8 +10,7 @@
 static inline int arch_spin_is_locked(arch_spinlock_t *x)
 {
 	volatile unsigned int *a = __ldcw_align(x);
-	smp_mb();
-	return *a == 0;
+	return READ_ONCE(*a) == 0;
 }

 static inline void arch_spin_lock(arch_spinlock_t *x)
@@ -21,22 +20,21 @@ static inline void arch_spin_lock(arch_spinlock_t *x)
 	a = __ldcw_align(x);
 	while (__ldcw(a) == 0)
 		while (*a == 0)
-			cpu_relax();
+			continue;
 }

 static inline void arch_spin_lock_flags(arch_spinlock_t *x,
-					 unsigned long flags)
+					  unsigned long flags)
 {
 	volatile unsigned int *a;
-	unsigned long flags_dis;

 	a = __ldcw_align(x);
 	while (__ldcw(a) == 0) {
-		local_save_flags(flags_dis);
-		local_irq_restore(flags);
 		while (*a == 0)
-			cpu_relax();
-		local_irq_restore(flags_dis);
+			if (flags & PSW_SM_I) {
+				local_irq_enable();
+				local_irq_disable();
+			}
 	}
 }
 #define arch_spin_lock_flags arch_spin_lock_flags
@@ -46,23 +44,15 @@ static inline void arch_spin_unlock(arch_spinlock_t *x)
 	volatile unsigned int *a;

 	a = __ldcw_align(x);
-#ifdef CONFIG_SMP
-	(void) __ldcw(a);
-#else
-	mb();
-#endif
-	*a = 1;
+	asm volatile("stw,ma %0,0(%1)" : : "r"(1), "r"(a) : "memory");
 }

 static inline int arch_spin_trylock(arch_spinlock_t *x)
 {
 	volatile unsigned int *a;
-	int ret;

 	a = __ldcw_align(x);
-        ret = __ldcw(a) != 0;
-
-	return ret;
+	return __ldcw(a) != 0;
 }

 /*


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2020-07-21 12:59 [PATCH v2] parisc: Various spin lock optimizations John David Anglin

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