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From: "Pankaj Dubey" <pankaj.dubey@samsung.com>
To: "'Gustavo Pimentel'" <Gustavo.Pimentel@synopsys.com>,
	<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <jingoohan1@gmail.com>, <lorenzo.pieralisi@arm.com>,
	<bhelgaas@google.com>, "'Anvesh Salveru'" <anvesh.s@samsung.com>
Subject: RE: [PATCH 1/2] PCI: dwc: Add support to disable GEN3 equalization
Date: Fri, 13 Sep 2019 16:23:41 +0530
Message-ID: <002701d56a21$82a4c880$87ee5980$@samsung.com> (raw)
In-Reply-To: <DM6PR12MB4010B4CC5DD11D3607D157ABDAB00@DM6PR12MB4010.namprd12.prod.outlook.com>



> -----Original Message-----
> From: Gustavo Pimentel <Gustavo.Pimentel@synopsys.com>
> Sent: Thursday, September 12, 2019 7:52 PM
> To: Pankaj Dubey <pankaj.dubey@samsung.com>; linux-pci@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Cc: jingoohan1@gmail.com; Gustavo.Pimentel@synopsys.com;
> lorenzo.pieralisi@arm.com; bhelgaas@google.com; Anvesh Salveru
> <anvesh.s@samsung.com>
> Subject: RE: [PATCH 1/2] PCI: dwc: Add support to disable GEN3 equalization
> 
> Hi,
> 
> On Tue, Sep 10, 2019 at 13:25:1, Pankaj Dubey <pankaj.dubey@samsung.com>
> wrote:
> 
> > From: Anvesh Salveru <anvesh.s@samsung.com>
> >
> > In some platforms, PCIe PHY may have issues which will prevent linkup
> > to happen in GEN3 or high speed. In case equalization fails, link will
> > fallback to GEN1.
> >
> > Designware controller has support for disabling GEN3 equalization if
> > required. This patch enables the designware driver to disable the PCIe
> > GEN3 equalization by writing into PCIE_PORT_GEN3_RELATED.
> 
> s/Designware/DesignWare
> s/designware/DesignWare
> 
> >
> > Platform drivers can disable equalization by setting the dwc_pci_quirk
> > flag DWC_EQUALIZATION_DISABLE.
> >
> > Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com>
> > Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> > ---
> >  drivers/pci/controller/dwc/pcie-designware.c | 7 +++++++
> > drivers/pci/controller/dwc/pcie-designware.h | 7 +++++++
> >  2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.c
> > b/drivers/pci/controller/dwc/pcie-designware.c
> > index 7d25102..bf82091 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.c
> > +++ b/drivers/pci/controller/dwc/pcie-designware.c
> > @@ -466,4 +466,11 @@ void dw_pcie_setup(struct dw_pcie *pci)
> >  		break;
> >  	}
> >  	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
> > +
> > +	val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED);
> > +
> > +	if (pci->dwc_pci_quirk & DWC_EQUALIZATION_DISABLE)
> > +		val |= PORT_LOGIC_GEN3_EQ_DISABLE;
> > +
> > +	dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val);
> >  }
> > diff --git a/drivers/pci/controller/dwc/pcie-designware.h
> > b/drivers/pci/controller/dwc/pcie-designware.h
> > index ffed084..a1453c5 100644
> > --- a/drivers/pci/controller/dwc/pcie-designware.h
> > +++ b/drivers/pci/controller/dwc/pcie-designware.h
> > @@ -29,6 +29,9 @@
> >  #define LINK_WAIT_MAX_IATU_RETRIES	5
> >  #define LINK_WAIT_IATU			9
> >
> > +/* Parameters for PCIe Quirks */
> > +#define DWC_EQUALIZATION_DISABLE	0x1
> > +
> >  /* Synopsys-specific PCIe configuration registers */
> >  #define PCIE_PORT_LINK_CONTROL		0x710
> >  #define PORT_LINK_MODE_MASK		GENMASK(21, 16)
> > @@ -60,6 +63,9 @@
> >  #define PCIE_MSI_INTR0_MASK		0x82C
> >  #define PCIE_MSI_INTR0_STATUS		0x830
> >
> > +#define PCIE_PORT_GEN3_RELATED		0x890
> > +#define PORT_LOGIC_GEN3_EQ_DISABLE	BIT(16)
> > +
> >  #define PCIE_ATU_VIEWPORT		0x900
> >  #define PCIE_ATU_REGION_INBOUND		BIT(31)
> >  #define PCIE_ATU_REGION_OUTBOUND	0
> > @@ -244,6 +250,7 @@ struct dw_pcie {
> >  	struct dw_pcie_ep	ep;
> >  	const struct dw_pcie_ops *ops;
> >  	unsigned int		version;
> > +	unsigned int		dwc_pci_quirk;
> 
> I'd prefer called this variable just quirk, the prefix is redundant here.
> 
> >  };
> >
> >  #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie,
> > pp)
> > --
> > 2.7.4
> 
> I understand your idea and I'm fine with it, but I just wonder if there isn't any
> other typical way to do this kind of quirks... I'm not seeing a similar case to this
> although.

Even we didn't see any existing approach to address this.

> For me makes more sense to squash both patches (1 and 2), since we aim to add
> this quirk especially because it focuses is on this "GEN3_RELATED"
> register in a logical patch.
>

Done. Posted [v2] where we squashed both the patches.
v2: https://lkml.org/lkml/2019/9/13/171

Thanks for review.
 
> Regards,
> Gustavo


      reply index

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20190910122514epcas5p4f00c0f999333dd7707c0a353fd06b57f@epcas5p4.samsung.com>
2019-09-10 12:25 ` Pankaj Dubey
     [not found]   ` <CGME20190910122520epcas5p1faeb16f7c38ee057ce93783a637e6bf4@epcas5p1.samsung.com>
2019-09-10 12:25     ` [PATCH 2/2] PCI: dwc: Add support to disable equalization phase 2 and 3 Pankaj Dubey
2019-09-10 14:05       ` Andrew Murray
2019-09-10 16:21         ` Pankaj Dubey
2019-09-11  9:27           ` Andrew Murray
2019-09-12 11:44             ` Pankaj Dubey
2019-09-10 13:58   ` [PATCH 1/2] PCI: dwc: Add support to disable GEN3 equalization Andrew Murray
2019-09-10 16:16     ` Pankaj Dubey
2019-09-11  9:23       ` Andrew Murray
2019-09-12 11:39         ` Pankaj Dubey
2019-09-12 12:42           ` Andrew Murray
2019-09-12 14:21   ` Gustavo Pimentel
2019-09-13 10:53     ` Pankaj Dubey [this message]

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