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[95.247.89.122]) by smtp.gmail.com with ESMTPSA id s11sm36459960wms.5.2020.05.13.05.54.44 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 May 2020 05:54:45 -0700 (PDT) From: To: "'Stanimir Varbanov'" , "'Bjorn Andersson'" Cc: "'Sham Muthayyan'" , "'Andy Gross'" , "'Bjorn Helgaas'" , "'Rob Herring'" , "'Mark Rutland'" , "'Lorenzo Pieralisi'" , "'Andrew Murray'" , "'Philipp Zabel'" , , , , References: <20200430220619.3169-1-ansuelsmth@gmail.com> <20200430220619.3169-10-ansuelsmth@gmail.com> <3dc89ec6-d550-9402-1a4a-ca0c6f1e1fb9@mm-sol.com> In-Reply-To: <3dc89ec6-d550-9402-1a4a-ca0c6f1e1fb9@mm-sol.com> Subject: R: [PATCH v3 09/11] PCI: qcom: add ipq8064 rev2 variant and set tx term offset Date: Wed, 13 May 2020 14:54:41 +0200 Message-ID: <02df01d62925$acd160a0$067421e0$@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Content-Language: it Thread-Index: AQH0plL6ngkayUAAEEU7BifA9vEwhgKDdr3rAu/CbUKoPWRmMA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org > Hi Ansuel, > > On 5/1/20 1:06 AM, Ansuel Smith wrote: > > From: Sham Muthayyan > > > > Add tx term offset support to pcie qcom driver need in some revision of > > the ipq806x SoC. > > Ipq8064 have tx term offset set to 7. > > Ipq8064-v2 revision and ipq8065 have the tx term offset set to 0. > > > > Signed-off-by: Sham Muthayyan > > Signed-off-by: Ansuel Smith > > --- > > drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++++ > > 1 file changed, 15 insertions(+) > > > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c > b/drivers/pci/controller/dwc/pcie-qcom.c > > index da8058fd1925..372d2c8508b5 100644 > > --- a/drivers/pci/controller/dwc/pcie-qcom.c > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > > @@ -45,6 +45,9 @@ > > #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10 > > > > #define PCIE20_PARF_PHY_CTRL 0x40 > > +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(12, > 16) > > The mask definition is not correct. Should be GENMASK(20, 16) > > > +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16) > > + > > #define PCIE20_PARF_PHY_REFCLK 0x4C > > #define PHY_REFCLK_SSP_EN BIT(16) > > #define PHY_REFCLK_USE_PAD BIT(12) > > @@ -118,6 +121,7 @@ struct qcom_pcie_resources_2_1_0 { > > u32 tx_swing_full; > > u32 tx_swing_low; > > u32 rx0_eq; > > + u8 phy_tx0_term_offset; > > }; > > > > struct qcom_pcie_resources_1_0_0 { > > @@ -318,6 +322,11 @@ static int > qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) > > if (IS_ERR(res->ext_reset)) > > return PTR_ERR(res->ext_reset); > > > > + if (of_device_is_compatible(dev->of_node, "qcom,pcie-ipq8064")) > > + res->phy_tx0_term_offset = 7; > > Before your change the phy_tx0_term_offser was 0 for apq8064, but here > you change it to 7, why? > apq8064 board should use qcom,pcie-apq8064 right? This should be set to 0 only with pcie-ipq8064 compatible. Tell me if I'm wrong. > > + else > > + res->phy_tx0_term_offset = 0; > > + > > res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); > > return PTR_ERR_OR_ZERO(res->phy_reset); > > } > > @@ -402,6 +411,11 @@ static int qcom_pcie_init_2_1_0(struct > qcom_pcie *pcie) > > /* enable PCIe clocks and resets */ > > qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, > BIT(0), 0); > > > > + /* set TX termination offset */ > > + qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, > > + PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, > > As the mask definition is incorrect you actually clear 12 to 16 bit in > the register where is another PHY parameter. Is that was intentional? > Will check this and the wrong genmask. > > + PHY_CTRL_PHY_TX0_TERM_OFFSET(res- > >phy_tx0_term_offset)); > > + > > writel(PCS_DEEMPH_TX_DEEMPH_GEN1(res->tx_deemph_gen1) | > > PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(res- > >tx_deemph_gen2_3p5db) | > > PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(res- > >tx_deemph_gen2_6db), > > @@ -1485,6 +1499,7 @@ static int qcom_pcie_probe(struct > platform_device *pdev) > > static const struct of_device_id qcom_pcie_match[] = { > > { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 }, > > { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 }, > > + { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 }, > > { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 }, > > { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 }, > > { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 }, > > > > -- > regards, > Stan