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charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20201218153043epcas5p1831d9bc440e9e05609792f19dfeb4012 References: <1608305434-31685-1-git-send-email-shradha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org > From: Rob Herring > Subject: Re: =5BPATCH=5D PCI: dwc: Add upper limit address for outbound i= ATU >=20 > On Sun, Dec 20, 2020 at 6:56 PM Shradha Todi > wrote: > > > > The size parameter is unsigned long type which can accept size > 4GB. > > In that case, the upper limit address must be programmed. Add support > > to program the upper limit address and set INCREASE_REGION_SIZE in > > case size > 4GB. >=20 > Not all DWC h/w versions have the upper register and bit. Is it safe to w= rite to > the non-existent register? Thanks for the review. Surely it exists post 4.80a version of controller but I am not sure in=20 which version of the controller this was introduced. I can figure this out from the SNPS team and update the patch accordingly. >=20 > > > > Signed-off-by: Shradha Todi > > --- > > drivers/pci/controller/dwc/pcie-designware.c =7C 8 ++++++-- > > drivers/pci/controller/dwc/pcie-designware.h =7C 1 + > > 2 files changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c > > b/drivers/pci/controller/dwc/pcie-designware.c > > index 28c56a1..7eba3b2 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.c > > +++ b/drivers/pci/controller/dwc/pcie-designware.c > > =40=40 -290,12 +290,16 =40=40 static void __dw_pcie_prog_outbound_atu(s= truct > dw_pcie *pci, u8 func_no, > > upper_32_bits(cpu_addr)); > > dw_pcie_writel_dbi(pci, PCIE_ATU_LIMIT, > > lower_32_bits(cpu_addr + size - 1)); > > + dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_LIMIT, > > + upper_32_bits(cpu_addr + size - 1)); >=20 > If not safe, perhaps only write if non-zero. >=20 Writing zero has no side-affect and we have tested this. > > dw_pcie_writel_dbi(pci, PCIE_ATU_LOWER_TARGET, > > lower_32_bits(pci_addr)); > > dw_pcie_writel_dbi(pci, PCIE_ATU_UPPER_TARGET, > > upper_32_bits(pci_addr)); > > - dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, type =7C > > - PCIE_ATU_FUNC_NUM(func_no)); > > + val =3D type =7C PCIE_ATU_FUNC_NUM(func_no); > > + val =3D upper_32_bits(size - 1) ? > > + val =7C PCIE_ATU_INCREASE_REGION_SIZE : val; > > + dw_pcie_writel_dbi(pci, PCIE_ATU_CR1, val); > > dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, PCIE_ATU_ENABLE); > > > > /* > > diff --git a/drivers/pci/controller/dwc/pcie-designware.h > > b/drivers/pci/controller/dwc/pcie-designware.h > > index b09329b..28b72fb 100644 > > --- a/drivers/pci/controller/dwc/pcie-designware.h > > +++ b/drivers/pci/controller/dwc/pcie-designware.h > > =40=40 -106,6 +106,7 =40=40 > > =23define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23= , 19), x) > > =23define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x= ) > > =23define PCIE_ATU_UPPER_TARGET 0x91C > > +=23define PCIE_ATU_UPPER_LIMIT 0x924 > > > > =23define PCIE_MISC_CONTROL_1_OFF 0x8BC > > =23define PCIE_DBI_RO_WR_EN BIT(0) > > -- > > 2.7.4 > >