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From: Gavin Shan <shangw@linux.vnet.ibm.com>
To: linux-pci@vger.kernel.org
Cc: bhelgaas@google.com, benh@kernel.crashing.org,
	linuxram@us.ibm.com, Gavin Shan <shangw@linux.vnet.ibm.com>
Subject: [PATCH 8/8] ppc/pnv: I/O and memory alignment for p2p bridges
Date: Wed, 25 Jul 2012 09:49:57 +0800	[thread overview]
Message-ID: <1343180997-9483-9-git-send-email-shangw@linux.vnet.ibm.com> (raw)
In-Reply-To: <1343180997-9483-1-git-send-email-shangw@linux.vnet.ibm.com>

The patch implements ppc_md.pcibios_window_alignment for powernv
platform so that the resource reassignment in PCI core will be
done according to the I/O and memory alignment returned from
powernv platform. The alignments returned from powernv platform
is closely depending on the scheme for PE segmenting. Besides,
the patch isn't useful for now, but the subsequent patches will
be working based on it.

Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
 arch/powerpc/platforms/powernv/pci-ioda.c |   38 +++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index fbdd74d..159bce5 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -1139,6 +1139,43 @@ static void __devinit pnv_pci_ioda_fixup_phb(struct pci_controller *hose)
 	}
 }
 
+/*
+ * Returns the alignment for I/O or memory windows for p2p
+ * bridges. That actually depends on how PEs are segmented.
+ * For now, we return I/O or M32 segment size for PE sensitive
+ * p2p bridges. Otherwise, the default values (4KiB for I/O,
+ * 1MiB for memory) will be returned.
+ */
+static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
+						unsigned long type)
+{
+	struct pci_dev *dev = bus->self;
+	struct pci_controller *hose = pci_bus_to_host(bus);
+	struct pnv_phb *phb = hose->private_data;
+
+	/* PCI root bus will be assigned with segment size */
+	if (!dev)
+		goto out;
+
+	/*
+	 * If the parent bridge is PCI bridge, we will return
+	 * the default values
+	 */
+	dev = dev->bus->self;
+	if (!dev)
+		goto out;
+	if (dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
+		return 1;
+	}
+
+out:
+	/* We need support prefetchable memory window later */
+	if (type & IORESOURCE_MEM)
+		return phb->ioda.m32_segsize;
+
+	return phb->ioda.io_segsize;
+}
+
 /* Prevent enabling devices for which we couldn't properly
  * assign a PE
  */
@@ -1306,6 +1343,7 @@ void __init pnv_pci_init_ioda1_phb(struct device_node *np)
 	 */
 	ppc_md.pcibios_fixup_phb = pnv_pci_ioda_fixup_phb;
 	ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
+	ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
 	pci_add_flags(PCI_PROBE_ONLY | PCI_REASSIGN_ALL_RSRC);
 
 	/* Reset IODA tables to a clean state */
-- 
1.7.5.4


  parent reply	other threads:[~2012-07-25  1:50 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-07-25  1:49 [PATCH Resend v7 0/8] minimal alignment for p2p bars Gavin Shan
2012-07-25  1:49 ` [PATCH 1/8] pci: change variable name for find_pci_host_bridge Gavin Shan
2012-07-25  1:49 ` [PATCH 2/8] pci: argument pci_bus " Gavin Shan
2012-07-25  1:49 ` [PATCH 3/8] fiddle with conversion of pci and CPU address Gavin Shan
2012-08-17  3:20   ` Wei Yang
2012-07-25  1:49 ` [PATCH 4/8] pci: weak function returns alignment Gavin Shan
2012-08-17  3:00   ` Wei Yang
2012-07-25  1:49 ` [PATCH 5/8] pci: resource assignment based on p2p alignment Gavin Shan
2012-07-25  1:49 ` [PATCH 6/8] pci: refactor function pbus_size_mem Gavin Shan
2012-07-25  1:49 ` [PATCH 7/8] ppc/pci: override pcibios_window_alignment Gavin Shan
2012-07-25  1:49 ` Gavin Shan [this message]
2012-08-17  2:49   ` [PATCH 8/8] ppc/pnv: I/O and memory alignment for p2p bridges Wei Yang
2012-08-20 13:46 [PATCH V8 0/8] Minimal alignment for p2p bars Gavin Shan
2012-08-20 13:46 ` [PATCH 8/8] ppc/pnv: I/O and memory alignment for p2p bridges Gavin Shan

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