From: Jiang Liu <liuj97@gmail.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Don Dutile <ddutile@redhat.com>,
Mark Einon <mark.einon@gmail.com>
Cc: Jiang Liu <jiang.liu@huawei.com>, Yinghai Lu <yinghai@kernel.org>,
Taku Izumi <izumi.taku@jp.fujitsu.com>,
"Rafael J . Wysocki" <rjw@sisk.pl>,
Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>,
Yijing Wang <wangyijing@huawei.com>,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
Jiang Liu <liuj97@gmail.com>
Subject: [PATCH v3 31/32] PCI/et131x: use PCIe capabilities access functions to simplify implementation
Date: Wed, 1 Aug 2012 23:54:36 +0800 [thread overview]
Message-ID: <1343836477-7287-32-git-send-email-jiang.liu@huawei.com> (raw)
In-Reply-To: <1343836477-7287-1-git-send-email-jiang.liu@huawei.com>
From: Jiang Liu <jiang.liu@huawei.com>
Use PCIe capabilities access functions to simplify et131x driver's
implementation.
Signed-off-by: Jiang Liu <liuj97@gmail.com>
---
drivers/staging/et131x/et131x.c | 19 +++++--------------
1 file changed, 5 insertions(+), 14 deletions(-)
diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 5b11c5e..7c2e781 100644
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -4001,16 +4001,14 @@ static void et131x_hwaddr_init(struct et131x_adapter *adapter)
static int et131x_pci_init(struct et131x_adapter *adapter,
struct pci_dev *pdev)
{
- int cap = pci_pcie_cap(pdev);
u16 max_payload;
- u16 ctl;
int i, rc;
rc = et131x_init_eeprom(adapter);
if (rc < 0)
goto out;
- if (!cap) {
+ if (!pci_is_pcie(pdev)) {
dev_err(&pdev->dev, "Missing PCIe capabilities\n");
goto err_out;
}
@@ -4018,7 +4016,7 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
/* Let's set up the PORT LOGIC Register. First we need to know what
* the max_payload_size is
*/
- if (pci_read_config_word(pdev, cap + PCI_EXP_DEVCAP, &max_payload)) {
+ if (pci_pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) {
dev_err(&pdev->dev,
"Could not read PCI config space for Max Payload Size\n");
goto err_out;
@@ -4055,17 +4053,10 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
}
/* Change the max read size to 2k */
- if (pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl)) {
+ if (pci_pcie_capability_change_word(pdev, PCI_EXP_DEVCTL,
+ 0x4 << 12, PCI_EXP_DEVCTL_READRQ)) {
dev_err(&pdev->dev,
- "Could not read PCI config space for Max read size\n");
- goto err_out;
- }
-
- ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | (0x04 << 12);
-
- if (pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl)) {
- dev_err(&pdev->dev,
- "Could not write PCI config space for Max read size\n");
+ "Couldn't change PCI config space for Max read size\n");
goto err_out;
}
--
1.7.9.5
next prev parent reply other threads:[~2012-08-01 16:00 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-08-01 15:54 [PATCH v3 00/32] provide interfaces to access PCIe capabilities registers Jiang Liu
2012-08-01 15:54 ` [PATCH v3 01/32] PCI: add pcie_flags_reg into struct pci_dev to cache PCIe capabilities register Jiang Liu
2012-08-01 15:54 ` [PATCH v3 02/32] PCI: introduce pci_pcie_type(dev) to replace pci_dev->pcie_type Jiang Liu
2012-08-01 15:54 ` [PATCH v3 03/32] PCI: remove unused field pcie_type from struct pci_dev Jiang Liu
2012-08-01 15:54 ` [PATCH v3 04/32] PCI: add PCIe capabilities access functions to hide differences among PCIe specs Jiang Liu
2012-08-01 15:54 ` [PATCH v3 05/32] PCI/core: use PCIe capabilities access functions to simplify implementation Jiang Liu
2012-08-01 15:54 ` [PATCH v3 06/32] PCI/hotplug: " Jiang Liu
2012-08-02 1:30 ` Kaneshige, Kenji
2012-08-01 15:54 ` [PATCH v3 07/32] PCI/portdrv: " Jiang Liu
2012-08-02 1:33 ` Kaneshige, Kenji
2012-08-01 15:54 ` [PATCH v3 08/32] PCI/pciehp: " Jiang Liu
2012-08-02 1:37 ` Kaneshige, Kenji
2012-08-01 15:54 ` [PATCH v3 09/32] PCI/PME: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 10/32] PCI/AER: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 11/32] PCI/ASPM: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 12/32] PCI/ARM: " Jiang Liu
2012-08-01 17:20 ` Stephen Warren
2012-08-02 5:58 ` Thierry Reding
2012-08-03 18:05 ` Stephen Warren
2012-08-01 15:54 ` [PATCH v3 13/32] PCI/MIPS: " Jiang Liu
2012-08-13 21:40 ` David Daney
2012-08-01 15:54 ` [PATCH v3 14/32] PCI/tile: " Jiang Liu
2012-08-01 21:07 ` Chris Metcalf
2012-08-01 15:54 ` [PATCH v3 15/32] PCI/r8169: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 16/32] PCI/broadcom: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 17/32] PCI/igb: " Jiang Liu
2012-08-02 22:12 ` Jeff Kirsher
2012-08-01 15:54 ` [PATCH v3 18/32] PCI/vxge: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 19/32] PCI/mlx4: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 20/32] PCI/niu: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 21/32] PCI/myri10ge: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 22/32] PCI/chelsio: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 23/32] PCI/atl1c: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 24/32] PCI/ath9k: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 25/32] PCI/iwl: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 26/32] PCI/mthca: " Jiang Liu
2012-08-02 21:46 ` Roland Dreier
2012-08-01 15:54 ` [PATCH v3 27/32] PCI/qib: " Jiang Liu
2012-08-01 17:30 ` Marciniszyn, Mike
2012-08-01 15:54 ` [PATCH v3 28/32] PCI/qla: " Jiang Liu
2012-08-01 15:54 ` [PATCH v3 29/32] PCI/radeon: " Jiang Liu
2012-08-01 16:04 ` Deucher, Alexander
2012-08-01 15:54 ` [PATCH v3 30/32] PCI/tsi721: " Jiang Liu
2012-08-09 14:16 ` Bounine, Alexandre
2012-08-01 15:54 ` Jiang Liu [this message]
2012-08-01 15:54 ` [PATCH v3 32/32] PCI/rtl8192e: " Jiang Liu
2012-08-14 4:25 ` [PATCH v3 00/32] provide interfaces to access PCIe capabilities registers Bjorn Helgaas
2012-08-14 15:46 ` Jiang Liu
2012-08-20 15:26 ` Jiang Liu
2012-08-20 15:35 ` Bjorn Helgaas
2012-08-20 15:47 ` Jiang Liu
2012-08-20 16:10 ` Bjorn Helgaas
2012-08-20 22:13 ` Bjorn Helgaas
2012-08-21 4:40 ` Cui, Dexuan
2012-08-22 16:28 ` Bjorn Helgaas
2012-08-23 1:00 ` Cui, Dexuan
2012-08-23 1:51 ` Don Dutile
2012-08-21 15:59 ` Jiang Liu
2012-08-22 17:08 ` Bjorn Helgaas
2012-08-24 18:52 ` Bjorn Helgaas
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