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From: Gavin Shan <shangw@linux.vnet.ibm.com>
To: linux-pci@vger.kernel.org
Cc: bhelgaas@google.com, benh@kernel.crashing.org,
	Gavin Shan <shangw@linux.vnet.ibm.com>
Subject: [PATCH 4/5] ppc/pci: override pcibios_window_alignment
Date: Fri,  7 Sep 2012 13:00:34 +0800	[thread overview]
Message-ID: <1346994035-16218-5-git-send-email-shangw@linux.vnet.ibm.com> (raw)
In-Reply-To: <1346994035-16218-1-git-send-email-shangw@linux.vnet.ibm.com>

Function pcibios_window_alignment() has been implemented as "weak"
in PCI core to return the default alignment of I/O and memory windows
for the associated p2p bridge. The patch adds same function to
override the weak one so that the default alignment could be changed
for those platforms (e.g. powernv).

Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/machdep.h |    3 +++
 arch/powerpc/kernel/pci-common.c   |   20 ++++++++++++++++++++
 2 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index 42ce570..f7706d7 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -214,6 +214,9 @@ struct machdep_calls {
 	/* Called after scan and before resource survey */
 	void (*pcibios_fixup_phb)(struct pci_controller *hose);
 
+	/* Called during PCI resource reassignment */
+	resource_size_t (*pcibios_window_alignment)(struct pci_bus *, unsigned long type);
+
 	/* Called to shutdown machine specific hardware not already controlled
 	 * by other drivers.
 	 */
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 2aa04f2..43fea54 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -99,6 +99,26 @@ void pcibios_free_controller(struct pci_controller *phb)
 		kfree(phb);
 }
 
+/*
+ * The function is used to return the minimal alignment
+ * for memory or I/O windows of the associated P2P bridge.
+ * By default, 4KiB alignment for I/O windows and 1MiB for
+ * memory windows.
+ */
+resource_size_t pcibios_window_alignment(struct pci_bus *bus,
+					 unsigned long type)
+{
+	if (ppc_md.pcibios_window_alignment)
+		return ppc_md.pcibios_window_alignment(bus, type);
+
+	/*
+	 * PCI core will figure out the default
+	 * alignment: 4KiB for I/O and 1MiB for
+	 * memory window.
+	 */
+	return 1;
+}
+
 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
 {
 #ifdef CONFIG_PPC64
-- 
1.7.5.4


  parent reply	other threads:[~2012-09-07  5:00 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-09-07  5:00 [PATCH V9 0/5] Minimal alignment for p2p bars Gavin Shan
2012-09-07  5:00 ` [PATCH 1/5] pci: weak function returns alignment Gavin Shan
2012-09-07  5:00 ` [PATCH 2/5] pci: resource assignment based on p2p alignment Gavin Shan
2012-09-07  5:00 ` [PATCH 3/5] pci: refactor function pbus_size_mem Gavin Shan
2012-09-07  5:00 ` Gavin Shan [this message]
2012-09-07  5:00 ` [PATCH 5/5] ppc/pnv: I/O and memory alignment for p2p bridges Gavin Shan
2012-09-07 22:49 ` [PATCH V9 0/5] Minimal alignment for p2p bars Bjorn Helgaas
2012-09-07 23:51   ` Benjamin Herrenschmidt
2012-09-10 22:42     ` Bjorn Helgaas
2012-09-10 23:33       ` Benjamin Herrenschmidt

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