From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: linux-kernel@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>,
x86@kernel.org
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Subject: [PATCH 1/2] x86: intel_mid_pci: propagate actual return code
Date: Wed, 17 Jun 2015 22:03:49 +0300 [thread overview]
Message-ID: <1434567830-237840-2-git-send-email-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <1434567830-237840-1-git-send-email-andriy.shevchenko@linux.intel.com>
mp_map_gsi_to_irq() returns different codes if it fails.
intel_mid_pci_irq_enable() hides this under -EBUSY. The patch replaces it by
what is actually returned.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
arch/x86/pci/intel_mid_pci.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 2706230..0af2e78 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -210,10 +210,12 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
{
struct irq_alloc_info info;
int polarity;
+ int ret;
if (dev->irq_managed && dev->irq > 0)
return 0;
+ /* Set IRQ polarity */
if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
polarity = 0; /* active high */
else
@@ -224,8 +226,9 @@ static int intel_mid_pci_irq_enable(struct pci_dev *dev)
* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
* IOAPIC RTE entries, so we just enable RTE for the device.
*/
- if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info) < 0)
- return -EBUSY;
+ ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);
+ if (ret < 0)
+ return ret;
dev->irq_managed = 1;
--
2.1.4
next prev parent reply other threads:[~2015-06-17 19:03 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-06-17 19:03 [PATCH 0/2] x86: intel-mid-pci: fix to get eMMC detected Andy Shevchenko
2015-06-17 19:03 ` Andy Shevchenko [this message]
2015-06-17 19:03 ` [PATCH 2/2] x86: intel_mid_pci: work around for IRQ0 assignment Andy Shevchenko
2015-07-08 10:05 ` [PATCH 0/2] x86: intel-mid-pci: fix to get eMMC detected Andy Shevchenko
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