From: Lucas Stach <l.stach@pengutronix.de>
To: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
Cc: Jingoo Han <jingoohan1@gmail.com>,
Pratyush Anand <pratyush.anand@gmail.com>,
patchwork-lst@pengutronix.de, kernel@pengutronix.de
Subject: [PATCH v4 5/5] PCI: designware: set up high part of MSI target address
Date: Mon, 17 Aug 2015 13:06:18 +0200 [thread overview]
Message-ID: <1439809578-13654-6-git-send-email-l.stach@pengutronix.de> (raw)
In-Reply-To: <1439809578-13654-1-git-send-email-l.stach@pengutronix.de>
Set up the high part of the MSI target address in order to allow the
MSI target to reside above the 4GB mark on 64bit and PAE systems.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
v4: fix target address setup in dw_pcie_msi_init()
---
drivers/pci/host/pcie-designware.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 74034395cf2a..71629175d1a1 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -205,12 +205,16 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
void dw_pcie_msi_init(struct pcie_port *pp)
{
+ u64 msi_target;
+
pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
+ msi_target = virt_to_phys((void *)pp->msi_data);
/* program the msi_data */
dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
- virt_to_phys((void *)pp->msi_data));
- dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
+ (u32)(msi_target & 0xffffffff));
+ dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
+ (u32)(msi_target >> 32 & 0xffffffff));
}
static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
@@ -299,12 +303,15 @@ no_valid_irq:
static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
{
struct msi_msg msg;
+ u64 msi_target;
if (pp->ops->get_msi_addr)
- msg.address_lo = pp->ops->get_msi_addr(pp);
+ msi_target = pp->ops->get_msi_addr(pp);
else
- msg.address_lo = virt_to_phys((void *)pp->msi_data);
- msg.address_hi = 0x0;
+ msi_target = virt_to_phys((void *)pp->msi_data);
+
+ msg.address_lo = (u32)(msi_target & 0xffffffff);
+ msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
if (pp->ops->get_msi_data)
msg.data = pp->ops->get_msi_data(pp, pos);
--
2.4.6
next prev parent reply other threads:[~2015-08-17 11:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-08-17 11:06 [PATCH v4 0/5] Designware host multivector MSI and 64bit MSI fixes Lucas Stach
2015-08-17 11:06 ` [PATCH v4 1/5] PCI: allow MSI chip providers to implement their own multivector MSI setup Lucas Stach
2015-08-17 11:06 ` [PATCH v4 2/5] PCI: designware: factor out MSI msg setup Lucas Stach
2015-08-17 11:06 ` [PATCH v4 3/5] PCI: designware: implement multivector MSI irq setup Lucas Stach
2015-08-17 11:06 ` [PATCH v4 4/5] PCI: designware: change prototype of get_msi_addr Lucas Stach
2015-08-17 11:06 ` Lucas Stach [this message]
2015-08-18 3:52 ` [PATCH v4 5/5] PCI: designware: set up high part of MSI target address Pratyush Anand
2015-09-02 22:44 ` [PATCH v4 0/5] Designware host multivector MSI and 64bit MSI fixes Bjorn Helgaas
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