From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <bhelgaas@google.com>, <michals@xilinx.com>,
<lorenzo.pieralisi@arm.com>, <paul.burton@imgtec.com>,
<yinghai@kernel.org>, <wangyijing@huawei.com>, <robh@kernel.org>,
<russell.joyce@york.ac.uk>, <sorenb@xilinx.com>,
<jiang.liu@linux.intel.com>, <arnd@arndb.de>,
<pawel.moll@arm.com>, <mark.rutland@arm.com>,
<ijc+devicetree@hellion.org.uk>, <galak@codeaurora.org>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
"Bharat Kumar Gogada" <bharatku@xilinx.com>,
Ravi Kiran Gummaluri <rgummal@xilinx.com>
Subject: [PATCH V2 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node.
Date: Tue, 12 Jan 2016 23:06:12 +0530 [thread overview]
Message-ID: <1452620173-4905-5-git-send-email-bharatku@xilinx.com> (raw)
In-Reply-To: <1452620173-4905-1-git-send-email-bharatku@xilinx.com>
Updated Zynq PCI binding documentation with Microblaze node.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Adding Microblaze device tree node Documnetation.
---
.../devicetree/bindings/pci/xilinx-pcie.txt | 36 ++++++++++++++++++++--
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
index 02f979a..d207bf4 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -17,7 +17,10 @@ Required properties:
Please refer to the standard PCI bus binding document for a more
detailed explanation
-Optional properties:
+Optional properties for Zynq:
+- bus-range: PCI bus numbers covered
+
+Required property for Microblaze:
- bus-range: PCI bus numbers covered
Interrupt controller child node
@@ -38,13 +41,13 @@ the four INTx interrupts in ISR and route them to this domain.
Example:
++++++++
-
+Zynq:
pci_express: axi-pcie@50000000 {
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
compatible = "xlnx,axi-pcie-host-1.00.a";
- reg = < 0x50000000 0x10000000 >;
+ reg = < 0x50000000 0x1000000 >;
device_type = "pci";
interrupts = < 0 52 4 >;
interrupt-map-mask = <0 0 0 7>;
@@ -60,3 +63,30 @@ Example:
#interrupt-cells = <1>;
};
};
+
+
+Microblaze:
+ pci_express: axi-pcie@10000000 {
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ compatible = "xlnx,axi-pcie-host-1.00.a";
+ reg = <0x10000000 0x4000000>;
+ device_type = "pci";
+ interrupt-parent = <µbalze_0_intc>;
+ interrupts = <1 2>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc 1>,
+ <0 0 0 2 &pcie_intc 2>,
+ <0 0 0 3 &pcie_intc 3>,
+ <0 0 0 4 &pcie_intc 4>;
+ ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
+ bus-range = <0x00 0xff>;
+
+ pcie_intc: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ };
--
2.1.1
next prev parent reply other threads:[~2016-01-12 17:36 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-12 17:36 [PATCH V2 0/5] PCIe Xilinx generic driver for Microblaze and Bharat Kumar Gogada
2016-01-12 17:36 ` [PATCH V2 1/5] PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function Bharat Kumar Gogada
2016-01-12 17:36 ` [PATCH V2 2/5] PCI: xilinx: Removing struct hw_irq structure Bharat Kumar Gogada
2016-01-12 22:23 ` Arnd Bergmann
2016-01-27 14:27 ` Bharat Kumar Gogada
2016-01-12 17:36 ` [PATCH V2 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze Bharat Kumar Gogada
2016-01-12 22:27 ` Arnd Bergmann
2016-01-26 9:59 ` Michal Simek
2016-01-26 12:11 ` Arnd Bergmann
2016-01-26 15:21 ` Michal Simek
2016-01-27 14:41 ` Bharat Kumar Gogada
2016-01-27 14:33 ` Bharat Kumar Gogada
2016-01-27 15:14 ` Arnd Bergmann
2016-01-28 13:20 ` Bharat Kumar Gogada
2016-01-28 13:49 ` Arnd Bergmann
2016-01-28 14:18 ` Bharat Kumar Gogada
2016-01-28 14:23 ` Arnd Bergmann
2016-01-28 14:49 ` Lorenzo Pieralisi
2016-01-12 17:36 ` Bharat Kumar Gogada [this message]
2016-01-15 2:33 ` [PATCH V2 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node Rob Herring
2016-01-12 17:36 ` [PATCH V2 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver Bharat Kumar Gogada
2016-02-03 15:40 ` Bharat Kumar Gogada
2016-02-03 15:59 ` Bjorn Helgaas
2016-02-03 16:08 ` Bharat Kumar Gogada
2016-02-03 16:32 ` Bjorn Helgaas
2016-02-03 16:38 ` Bjorn Helgaas
2016-02-04 5:49 ` Bharat Kumar Gogada
2016-02-04 14:51 ` Bjorn Helgaas
2016-02-04 14:56 ` Bharat Kumar Gogada
2016-01-12 22:29 ` [PATCH V2 0/5] PCIe Xilinx generic driver for Microblaze and Arnd Bergmann
2016-01-27 14:35 ` Bharat Kumar Gogada
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