From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: <linux-pci@vger.kernel.org>, <bhelgaas@google.com>,
<jingoohan1@gmail.com>, <Joao.Pinto@synopsys.com>
Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers
Date: Thu, 6 Jul 2017 14:33:47 +0800 [thread overview]
Message-ID: <1499322829-23018-1-git-send-email-Zhiqiang.Hou@nxp.com> (raw)
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The read-only DBI registers can be written over the DBI when set
the "Write to RO Registers Using DBI" (DBI_RO_WR_EN) field of the
MISC_CONTROL_1_OFF register.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
drivers/pci/dwc/pcie-designware.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index b4d2a89..bbdf35b 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -76,6 +76,9 @@
#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
#define PCIE_ATU_UPPER_TARGET 0x91C
+#define PCIE_MISC_CONTROL_1_OFF 0x8BC
+#define PCIE_DBI_RO_WR_EN (0x1 << 0)
+
/*
* iATU Unroll-specific register definitions
* From 4.80 core version the address translation will be made by unroll
@@ -279,6 +282,28 @@ static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg)
return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4);
}
+static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
+{
+ u32 reg;
+ u32 val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dw_pcie_readl_dbi(pci, reg);
+ val |= PCIE_DBI_RO_WR_EN;
+ dw_pcie_writel_dbi(pci, reg, val);
+}
+
+static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
+{
+ u32 reg;
+ u32 val;
+
+ reg = PCIE_MISC_CONTROL_1_OFF;
+ val = dw_pcie_readl_dbi(pci, reg);
+ val &= ~PCIE_DBI_RO_WR_EN;
+ dw_pcie_writel_dbi(pci, reg, val);
+}
+
#ifdef CONFIG_PCIE_DW_HOST
irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
void dw_pcie_msi_init(struct pcie_port *pp);
--
2.1.0.27.g96db324
next reply other threads:[~2017-07-06 6:50 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-06 6:33 Zhiqiang Hou [this message]
2017-07-06 6:33 ` [PATCH 2/3] PCI: designware: enable write permission before updating class code Zhiqiang Hou
2017-07-06 6:33 ` [PATCH 3/3] PCI: layerscape: refactor the host_init function Zhiqiang Hou
2017-08-02 21:11 ` Bjorn Helgaas
2017-08-03 3:17 ` Z.q. Hou
2017-07-06 9:44 ` [PATCH 1/3] PCI: designware: add accessors for write permission of DBI read-only registers Joao Pinto
2017-07-07 3:48 ` Z.q. Hou
2017-07-07 8:53 ` Joao Pinto
2017-07-11 4:11 ` Z.q. Hou
2017-07-17 19:41 ` Jingoo Han
2017-07-18 3:00 ` Z.q. Hou
2017-08-02 21:25 ` Bjorn Helgaas
2017-08-03 3:25 ` Z.q. Hou
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