From: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
To: <linux-pci@vger.kernel.org>, <bhelgaas@google.com>,
<jingoohan1@gmail.com>, <Joao.Pinto@synopsys.com>
Cc: <minghuan.lian@nxp.com>, <mingkai.hu@nxp.com>, <roy.zang@nxp.com>,
Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Subject: [PATCHv2 4/6] PCI: layerscape: refactor the host_init function
Date: Thu, 3 Aug 2017 16:23:38 +0800 [thread overview]
Message-ID: <1501748620-42866-5-git-send-email-Zhiqiang.Hou@nxp.com> (raw)
In-Reply-To: <1501748620-42866-1-git-send-email-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Make the ls1021a's host_init reuse layerscape platform's common
host_init function.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
V2:
- Removed the disable outbound windows code and the remove duplicate class code
fixup code from this patch.
drivers/pci/dwc/pci-layerscape.c | 54 ++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 09056a6..3533a8c 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -107,33 +107,6 @@ static int ls1021_pcie_link_up(struct dw_pcie *pci)
return 1;
}
-static void ls1021_pcie_host_init(struct pcie_port *pp)
-{
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- struct ls_pcie *pcie = to_ls_pcie(pci);
- struct device *dev = pci->dev;
- u32 index[2];
-
- pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
- "fsl,pcie-scfg");
- if (IS_ERR(pcie->scfg)) {
- dev_err(dev, "No syscfg phandle specified\n");
- pcie->scfg = NULL;
- return;
- }
-
- if (of_property_read_u32_array(dev->of_node,
- "fsl,pcie-scfg", index, 2)) {
- pcie->scfg = NULL;
- return;
- }
- pcie->index = index[1];
-
- dw_pcie_setup_rc(pp);
-
- ls_pcie_drop_msg_tlp(pcie);
-}
-
static int ls_pcie_link_up(struct dw_pcie *pci)
{
struct ls_pcie *pcie = to_ls_pcie(pci);
@@ -160,6 +133,33 @@ static void ls_pcie_host_init(struct pcie_port *pp)
dw_pcie_dbi_ro_wr_dis(pci);
ls_pcie_drop_msg_tlp(pcie);
+
+ dw_pcie_setup_rc(pp);
+}
+
+static void ls1021_pcie_host_init(struct pcie_port *pp)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct ls_pcie *pcie = to_ls_pcie(pci);
+ struct device *dev = pci->dev;
+ u32 index[2];
+
+ pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "fsl,pcie-scfg");
+ if (IS_ERR(pcie->scfg)) {
+ dev_err(dev, "No syscfg phandle specified\n");
+ pcie->scfg = NULL;
+ return;
+ }
+
+ if (of_property_read_u32_array(dev->of_node,
+ "fsl,pcie-scfg", index, 2)) {
+ pcie->scfg = NULL;
+ return;
+ }
+ pcie->index = index[1];
+
+ ls_pcie_host_init(pp);
}
static int ls_pcie_msi_host_init(struct pcie_port *pp,
--
2.1.0.27.g96db324
next prev parent reply other threads:[~2017-08-03 8:40 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-03 8:23 [PATCHv2 0/6] PCI: fix the designware Class code fixup doesn't work issue and refactor ls-pcie host init Zhiqiang Hou
2017-08-03 8:23 ` [PATCHv2 1/6] PCI: designware: add accessors for write permission of DBI read-only registers Zhiqiang Hou
2017-08-08 12:45 ` Joao Pinto
2017-08-09 2:50 ` Z.q. Hou
2017-08-03 8:23 ` [PATCHv2 2/6] PCI: designware: enable write permission before updating class code Zhiqiang Hou
2017-08-08 12:45 ` Joao Pinto
2017-08-09 2:51 ` Z.q. Hou
2017-08-03 8:23 ` [PATCHv2 3/6] PCI: layerscape: use accessors to enable/disable DBI RO registers' write permission Zhiqiang Hou
2017-08-08 12:46 ` Joao Pinto
2017-08-09 2:52 ` Z.q. Hou
2017-08-03 8:23 ` Zhiqiang Hou [this message]
2017-08-08 13:13 ` [PATCHv2 4/6] PCI: layerscape: refactor the host_init function Joao Pinto
2017-08-09 2:53 ` Z.q. Hou
2017-08-14 21:38 ` Bjorn Helgaas
2017-08-14 22:26 ` Bjorn Helgaas
2017-08-15 3:21 ` Z.q. Hou
2017-08-15 9:34 ` Stanimir Varbanov
2017-08-16 5:19 ` Z.q. Hou
2017-08-15 3:05 ` Z.q. Hou
2017-08-03 8:23 ` [PATCHv2 5/6] PCI: layerscape: Disable the outbound windows configured by bootloader Zhiqiang Hou
2017-08-03 8:23 ` [PATCHv2 6/6] PCI: layerscape: remove the duplicate Class field fix code Zhiqiang Hou
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