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From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Thierry Reding <thierry.reding@gmail.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>, <mark.rutland@arm.com>,
	<jonathanh@nvidia.com>, <vidyas@nvidia.com>,
	<linux-tegra@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<devicetree@vger.kernel.org>
Subject: Re: [PATCH V4 27/28] PCI: tegra: Add support for GPIO based PERST#
Date: Fri, 14 Jun 2019 20:08:26 +0530
Message-ID: <1508173d-0ecc-f498-6ab2-78a718086b35@nvidia.com> (raw)
In-Reply-To: <20190614143222.GB23116@e121166-lin.cambridge.arm.com>



On 14-Jun-19 8:02 PM, Lorenzo Pieralisi wrote:
> On Fri, Jun 14, 2019 at 04:07:35PM +0530, Manikanta Maddireddy wrote:
>>
>> On 13-Jun-19 8:54 PM, Lorenzo Pieralisi wrote:
>>> On Tue, Jun 04, 2019 at 03:22:33PM +0200, Thierry Reding wrote:
>>>
>>> [...]
>>>
>>>>> +	} else {
>>>>> +		value = afi_readl(port->pcie, ctrl);
>>>>> +		value &= ~AFI_PEX_CTRL_RST;
>>>>> +		afi_writel(port->pcie, value, ctrl);
>>>>> +	}
>>>>>  
>>>>>  	usleep_range(1000, 2000);
>>>>>  
>>>>> -	value = afi_readl(port->pcie, ctrl);
>>>>> -	value |= AFI_PEX_CTRL_RST;
>>>>> -	afi_writel(port->pcie, value, ctrl);
>>>>> +	if (port->reset_gpiod) {
>>>>> +		gpiod_set_value(port->reset_gpiod, 1);
>>>> After this the port should be functional, right? I think it'd be better
>>>> to reverse the logic here and move the polarity of the GPIO into device
>>>> tree. gpiod_set_value() takes care of inverting the level internally if
>>>> the GPIO is marked as low-active in DT.
>>>>
>>>> The end result is obviously the same, but it makes the usage much
>>>> clearer. If somebody want to write a DT for their board, they will look
>>>> at the schematics and see a low-active reset line and may be tempted to
>>>> describe it as such in DT, but with your current code that would be
>>>> exactly the wrong way around.
>>> I agree with Thierry here, you should change the logic.
>>>
>>> Question: what's the advantage of adding GPIO reset support if that's
>>> architected already in port registers ? I am pretty sure there is a
>>> reason behind it (and forgive me the dumb question) and I would like to
>>> have it written in the commit log.
>>>
>>> Thanks,
>>> Lorenzo
>> Each PCIe controller has a dedicated SFIO pin to support PERST#
>> signal. Port register can control only this particular SFIO pin.
>> However, in one of the Nvidia platform, instead of using PCIe SFIO
>> pin, different gpio is routed PCIe slot. This happened because of a
>> confusion in IO ball naming convention. To support this particular
>> platform, driver has provide gpio support. I will update the commit
>> log in V5.
> What happens on that platform where you trigger reset through a port
> register with :
>
> value = afi_readl(port->pcie, ctrl);
> value |= AFI_PEX_CTRL_RST;
> afi_writel(port->pcie, value, ctrl);
>
> (imagine the DT is not updated for instance or on current
> mainline) ?
>
> Lorenzo

Lets take an example of PCIe controller-0, SFIO ball name which is controlled
by the port-0 register is PEX_L0_RST. It will deassert PEX_L0_RST SFIO line
but it doesn't go to PCIe slot, so fundamental reset(PERST# deassert) is not
applied to the endpoint connected to that slot.

Manikanta

>> Manikanta
>>
>>>>> +	} else {
>>>>> +		value = afi_readl(port->pcie, ctrl);
>>>>> +		value |= AFI_PEX_CTRL_RST;
>>>>> +		afi_writel(port->pcie, value, ctrl);
>>>>> +	}
>>>>>  }
>>>>>  
>>>>>  static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
>>>>> @@ -2238,6 +2249,7 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
>>>>>  		struct tegra_pcie_port *rp;
>>>>>  		unsigned int index;
>>>>>  		u32 value;
>>>>> +		char *label;
>>>>>  
>>>>>  		err = of_pci_get_devfn(port);
>>>>>  		if (err < 0) {
>>>>> @@ -2296,6 +2308,23 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
>>>>>  		if (IS_ERR(rp->base))
>>>>>  			return PTR_ERR(rp->base);
>>>>>  
>>>>> +		label = kasprintf(GFP_KERNEL, "pex-reset-%u", index);
>>>> devm_kasprintf()?
>>>>
>>>> Thierry
>>>>
>>>>> +		if (!label) {
>>>>> +			dev_err(dev, "failed to create reset GPIO label\n");
>>>>> +			return -ENOMEM;
>>>>> +		}
>>>>> +
>>>>> +		rp->reset_gpiod = devm_gpiod_get_from_of_node(dev, port,
>>>>> +							      "reset-gpios", 0,
>>>>> +							      GPIOD_OUT_LOW,
>>>>> +							      label);
>>>>> +		kfree(label);
>>>>> +		if (IS_ERR(rp->reset_gpiod)) {
>>>>> +			err = PTR_ERR(rp->reset_gpiod);
>>>>> +			dev_err(dev, "failed to get reset GPIO: %d\n", err);
>>>>> +			return err;
>>>>> +		}
>>>>> +
>>>>>  		list_add_tail(&rp->list, &pcie->ports);
>>>>>  	}
>>>>>  
>>>>> -- 
>>>>> 2.17.1
>>>>>


  reply index

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-16  5:52 [PATCH V4 00/28] Enable Tegra PCIe root port features Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 01/28] soc/tegra: pmc: Export tegra_powergate_power_on() Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 02/28] PCI: tegra: Handle failure cases in tegra_pcie_power_on() Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 03/28] PCI: tegra: Rearrange Tegra PCIe driver functions Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 04/28] PCI: tegra: Mask AFI_INTR in runtime suspend Manikanta Maddireddy
2019-06-04 13:08   ` Thierry Reding
2019-05-16  5:52 ` [PATCH V4 05/28] PCI: tegra: Fix PCIe host power up sequence Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 06/28] PCI: tegra: Add PCIe Gen2 link speed support Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 07/28] PCI: tegra: Advertise PCIe Advanced Error Reporting (AER) capability Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 08/28] PCI: tegra: Program UPHY electrical settings for Tegra210 Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 09/28] PCI: tegra: Enable opportunistic UpdateFC and ACK Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 10/28] PCI: tegra: Disable AFI dynamic clock gating Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 11/28] PCI: tegra: Process pending DLL transactions before entering L1 or L2 Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 12/28] PCI: tegra: Enable PCIe xclk clock clamping Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 13/28] PCI: tegra: Increase the deskew retry time Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 14/28] PCI: tegra: Add SW fixup for RAW violations Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 15/28] PCI: tegra: Update flow control timer frequency in Tegra210 Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 16/28] PCI: tegra: Set target speed as Gen1 before starting LTSSM Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 17/28] PCI: tegra: Fix PLLE power down issue due to CLKREQ# signal Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 18/28] PCI: tegra: Program AFI_CACHE* registers only for Tegra20 Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 19/28] PCI: tegra: Change PRSNT_SENSE IRQ log to debug Manikanta Maddireddy
2019-05-16  5:52 ` [PATCH V4 20/28] PCI: tegra: Use legacy IRQ for port service drivers Manikanta Maddireddy
2019-05-20 20:37   ` Bjorn Helgaas
2019-05-21  9:07     ` Manikanta Maddireddy
2019-05-16  5:53 ` [PATCH V4 21/28] PCI: tegra: Add AFI_PEX2_CTRL reg offset as part of soc struct Manikanta Maddireddy
2019-05-16  5:53 ` [PATCH V4 22/28] PCI: tegra: Access endpoint config only if PCIe link is up Manikanta Maddireddy
2019-06-04 13:14   ` Thierry Reding
2019-06-04 14:10     ` Manikanta Maddireddy
2019-06-10  4:38       ` Manikanta Maddireddy
2019-06-13 14:39         ` Lorenzo Pieralisi
2019-06-13 15:42           ` Thierry Reding
2019-06-17 10:01             ` Manikanta Maddireddy
2019-06-17 11:47               ` Thierry Reding
2019-06-17 19:30                 ` Bjorn Helgaas
2019-06-18  5:36                   ` Manikanta Maddireddy
2019-06-18 10:49                     ` Thierry Reding
2019-06-18 12:32                       ` Johannes Berg
2019-06-18 13:40                         ` Thierry Reding
2019-06-18 14:48                           ` Johannes Berg
2019-06-19 13:38                         ` Bjorn Helgaas
2019-06-19 13:40                           ` Johannes Berg
2019-05-16  5:53 ` [PATCH V4 23/28] dt-bindings: pci: tegra: Document PCIe DPD pinctrl optional prop Manikanta Maddireddy
2019-05-16  5:53 ` [PATCH V4 24/28] arm64: tegra: Add PEX DPD states as pinctrl properties Manikanta Maddireddy
2019-05-16  5:53 ` [PATCH V4 25/28] PCI: tegra: Put PEX CLK & BIAS pads in DPD mode Manikanta Maddireddy
2019-05-16  5:53 ` [PATCH V4 26/28] PCI: Add DT binding for "reset-gpios" property Manikanta Maddireddy
2019-06-17 11:30   ` Thierry Reding
2019-06-17 11:38     ` Manikanta Maddireddy
2019-06-17 11:48       ` Thierry Reding
2019-05-16  5:53 ` [PATCH V4 27/28] PCI: tegra: Add support for GPIO based PERST# Manikanta Maddireddy
2019-06-04 13:22   ` Thierry Reding
2019-06-13 15:24     ` Lorenzo Pieralisi
2019-06-14 10:37       ` Manikanta Maddireddy
2019-06-14 14:32         ` Lorenzo Pieralisi
2019-06-14 14:38           ` Manikanta Maddireddy [this message]
2019-06-14 14:50             ` Lorenzo Pieralisi
2019-06-14 14:56               ` Manikanta Maddireddy
2019-06-14 15:23               ` Thierry Reding
2019-06-14 15:59                 ` Lorenzo Pieralisi
2019-06-14 16:30                   ` Manikanta Maddireddy
2019-06-14 16:53                     ` Lorenzo Pieralisi
2019-06-14 17:23                       ` Manikanta Maddireddy
2019-06-17  9:48                         ` Lorenzo Pieralisi
2019-06-17 10:27                           ` Manikanta Maddireddy
2019-06-17 10:39                             ` Lorenzo Pieralisi
2019-06-17 11:29                         ` Thierry Reding
2019-06-17 11:26                       ` Thierry Reding
2019-05-16  5:53 ` [PATCH V4 28/28] PCI: tegra: Change link retry log level to debug Manikanta Maddireddy
2019-06-04 13:22   ` Thierry Reding
2019-05-16 13:12 ` [PATCH V4 00/28] Enable Tegra PCIe root port features Bjorn Helgaas
2019-05-17  8:38   ` Manikanta Maddireddy
2019-06-10  4:45 ` Manikanta Maddireddy
2019-06-10 17:33   ` Lorenzo Pieralisi

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