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From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>
Cc: <linux-pci@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Subject: [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming
Date: Mon, 11 Mar 2019 17:15:59 +0530
Message-ID: <1552304759-5394-1-git-send-email-bharat.kumar.gogada@xilinx.com> (raw)

The current Multi MSI data programming fails if multiple end points
requesting MSI and multi MSI are connected with switch, i.e the current
multi MSI data being given is not considering the number of vectors
being requested in case of multi MSI.
Due to this if multiple end points are connected and requesting MSI
and multi MSI combination, the multi MSI data is ending up using
wrong MSI data, which might be used by different device.

Fix Multi MSI data programming with required alignment by
using number of vectors being requested.

Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL PCIe
Host Controller")
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
---
V2:
 - Added more description of fix
---
 drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 81538d7..36669c5 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -484,7 +484,7 @@ static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 
 	mutex_lock(&msi->lock);
 	bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
-					 nr_irqs, 0);
+					 nr_irqs, nr_irqs - 1);
 	if (bit >= INT_PCI_MSI_NR) {
 		mutex_unlock(&msi->lock);
 		return -ENOSPC;
-- 
2.7.4


             reply index

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-11 11:45 Bharat Kumar Gogada [this message]
2019-04-01 17:00 ` Bharat Kumar Gogada
2019-04-02 16:08   ` Lorenzo Pieralisi
2019-04-04 11:48     ` Bharat Kumar Gogada
2019-04-02 16:23 ` Ard Biesheuvel
2019-04-04 11:51   ` Bharat Kumar Gogada

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