[RFC 1/2] dt-bindings: imx6q-pcie: Add support for i.MX8QM/QXP PCIe

[Richard Zhu <hongxing.zhu@nxp.com>]

Add codes needed to support i.MX8QM/QXP PCIe.
- HSIO(High Speed IO) subsystem is new defined on i.MX8QM/QXP.
  The PCIe and SATA modules are contained in the HSIO subsystem. There
  are two PCIe, one SATA controllers and three mixed lane PHYs on
  i.MX8QM. There are three use cases of the HSIO subsystem on i.MX8QM.
  1. PCIea 2 lanes and one SATA AHCI port.
  2. PCIea 1 lane, PCIeb 1 lane and one SATA AHCI port.
  3. PCIea 2 lanes, PCIeb 1 lane.
  i.MX8QXP only has PCIeb controller and one lane PHY.
  Use the hsio-cfg property to specify the different modes.
- The HSIO address map as viewed from system level is as shown below.
  address [31:24]    Local address    Target    Address Size
  5F                 0                HSIO      16MB
  60-6F              40-4F            HSIO      256MB
  70-7F              80-8F            HSIO      256MB
  The property local-addr is required to specify it.
- Both external OSC and internal PLL can be used as PCIe reference
  clock, use the ext_osc property to distinguish them.
- clock request GPIO for controlling the PCI reference clock request
  signal. And should be configure OD when L1SS maybe enabled later.
- One more power domain HSIO_GPIO and clock PCIE_PER are required by
  i.MX8QM/QXP PCIe.
  Add these specific properties to enable i.MX8QM/QXP PCIe.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 .../devicetree/bindings/pci/fsl,imx6q-pcie.txt      | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index a7f5f5a..f7586c9 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -10,6 +10,8 @@ Required properties:
 	- "fsl,imx6qp-pcie"
 	- "fsl,imx7d-pcie"
 	- "fsl,imx8mq-pcie"
+	- "fsl,imx8qm-pcie"
+	- "fsl,imx8qxp-pcie"
 - reg: base address and length of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
@@ -38,6 +40,10 @@ Optional properties:
   The regulator will be enabled when initializing the PCIe host and
   disabled either as part of the init process or when shutting down the
   host.
+- clkreq-gpio: Should specify the GPIO for controlling the PCI reference clock
+  request signal.
+- ext_osc: External OSC is used as PCIe reference clock or not. 0: Internal
+  PLL. 1: External OSC.
 
 Additional required properties for imx6sx-pcie:
 - clock names: Must include the following additional entries:
@@ -60,6 +66,21 @@ Additional required properties for imx8mq-pcie:
 - clock-names: Must include the following additional entries:
 	- "pcie_aux"
 
+Additional required properties for imx8qm/qxp pcie:
+- power-domains: Must be set to a phandle pointing to PCIE, PCIE_PHY power and
+  HSIO_GPIO domains
+- power-domain-names: Must be "pcie", "pcie_phy", "hsio_gpio"
+- clock-names: Must include the following additional entries:
+	- "pcie_per"
+- hsio-cfg: hsio configration mode when the pcie node is supported.
+  1: pciea 2 lanes and one sata ahci port.
+  2: pciea 1 lane, pcieb 1 lane and one sata ahci port.
+  3: pciea 2 lanes, pcieb 1 lane.
+- local-addr: the local address used in hsio module on i.MX8QM/QXP.
+	Example:
+		hsio-cfg = <2>;
+		local-addr = <0x80000000>;
+
 Example:
 
 	pcie@01000000 {
-- 
2.7.4