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Thu, 4 Apr 2019 19:55:45 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Thu, 04 Apr 2019 12:55:45 -0700 From: Vidya Sagar To: , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH V2 06/16] PCI: dwc: Add ext config space capability search API Date: Fri, 5 Apr 2019 01:24:33 +0530 Message-ID: <1554407683-31580-7-git-send-email-vidyas@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1554407683-31580-1-git-send-email-vidyas@nvidia.com> References: <1554407683-31580-1-git-send-email-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1554407750; bh=/oOMjC6IRlty2ycZZpMBrpRTZzHY6Oputw2iHNOnGqU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=oCIi8ILRHQtFl0d3qCxlvVEWgzgNcFZTtuLnhvo7c0wtsUx5Sy6TNi7zCwWZxrlcr BrfXv0/yyyjTxbdkxvFOcFdUnGmd565aCK+Q4t/mwWfkIIYXOeVACvwyR5ywhOtfHb gmNW8zznXgPdcIyb7KOk3tw0kZz18A8MSpzy6LOg2ExhDlbVNYDOAKhDUCiWyKmfNf mnMa4o9LJGLXkTOQRCLVNrry1sRGlXoPuUoIUBZdtrGz8nGVf3hFNtvPYr8oK51Uct IMnUblC77cyXY8kab0dsYediZ3mdXU19eusWE2yxHWtZfZBfqPa5d4IVhs/ZZvHWgI uPxukttgfD6ZQ== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add extended configuration space capability search API using struct dw_pcie * pointer Signed-off-by: Vidya Sagar --- Changes from [v1]: * This is a new patch in v2 series drivers/pci/controller/dwc/pcie-designware.c | 41 ++++++++++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 42 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index d68c123e409c..44c0ba078452 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap) return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap); } +static int dw_pcie_find_next_ext_capability(struct dw_pcie *pci, int start, + int cap) +{ + u32 header; + int ttl; + int pos = PCI_CFG_SPACE_SIZE; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (start) + pos = start; + + header = dw_pcie_readl_dbi(pci, pos); + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap && pos != start) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (pos < PCI_CFG_SPACE_SIZE) + break; + + header = dw_pcie_readl_dbi(pci, pos); + } + + return 0; +} + +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap) +{ + return dw_pcie_find_next_ext_capability(pci, 0, cap); +} +EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability); + int dw_pcie_read(void __iomem *addr, int size, u32 *val) { if (!IS_ALIGNED((uintptr_t)addr, size)) { diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 4ccd4c706ddb..fa41d675c48f 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -248,6 +248,7 @@ struct dw_pcie { container_of((endpoint), struct dw_pcie, ep) u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap); +int dw_pcie_find_ext_capability(struct dw_pcie *pci, int cap); int dw_pcie_read(void __iomem *addr, int size, u32 *val); int dw_pcie_write(void __iomem *addr, int size, u32 val); -- 2.7.4