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* [PATCH v6 0/4] PCI: Patch series to support Thunderbolt without any BIOS support
@ 2019-05-22 14:30 Nicholas Johnson
  2019-06-15 19:56 ` Bjorn Helgaas
  0 siblings, 1 reply; 4+ messages in thread
From: Nicholas Johnson @ 2019-05-22 14:30 UTC (permalink / raw)
  To: linux-kernel
  Cc: linux-pci, bhelgaas, mika.westerberg, corbet, Nicholas Johnson

Rebase patches to apply cleanly to 5.2-rc1 source. Remove patch for 
comment style cleanup as this has already been applied.

Anybody interested in testing, you can do so with:

a) Intel system with Thunderbolt 3 and native enumeration. The Gigabyte 
Z390 Designare is one of the most perfect for this that I have never had 
the opportunity to use - it does not even have the option for BIOS 
assisted enumeration present in the BIOS.

b) Any system with PCIe and the Gigabyte GC-TITAN RIDGE add-in card, 
jump the header as described and use kernel parameters like:

pci=assign-busses,hpbussize=0x33,realloc,hpmemsize=128M,hpmemprefsize=1G,nocrs 
pcie_ports=native

[optional] pci.dyndbg

    ___
 __/   \__
|o o o o o| When looking into the receptacle on back of PCIe card.
|_________| Jump pins 3 and 5.

 1 2 3 4 5

The Intel system is nice in that it should just work. The add-in card 
setup is nice in that you can go nuts and assign copious amounts of 
MMIO_PREF - can anybody show a Xeon Phi coprocessor with 16G BAR working 
in an eGPU enclosure with these patches?

However, if you specify the above kernel parameters on the Intel system, 
you should be able to override it to allocate more space.

Nicholas Johnson (4):
  PCI: Consider alignment of hot-added bridges when distributing
    available resources
  PCI: Modify extend_bridge_window() to set resource size directly
  PCI: Fix bug resulting in double hpmemsize being assigned to MMIO
    window
  PCI: Add pci=hpmemprefsize parameter to set MMIO_PREF size
    independently

 .../admin-guide/kernel-parameters.txt         |   7 +-
 drivers/pci/pci.c                             |  18 +-
 drivers/pci/setup-bus.c                       | 265 ++++++++++--------
 include/linux/pci.h                           |   3 +-
 4 files changed, 167 insertions(+), 126 deletions(-)

-- 
2.20.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v6 0/4] PCI: Patch series to support Thunderbolt without any BIOS support
  2019-05-22 14:30 [PATCH v6 0/4] PCI: Patch series to support Thunderbolt without any BIOS support Nicholas Johnson
@ 2019-06-15 19:56 ` Bjorn Helgaas
  2019-06-17 16:55   ` Logan Gunthorpe
  2019-07-01 14:33   ` Nicholas Johnson
  0 siblings, 2 replies; 4+ messages in thread
From: Bjorn Helgaas @ 2019-06-15 19:56 UTC (permalink / raw)
  To: Nicholas Johnson
  Cc: linux-kernel, linux-pci, mika.westerberg, corbet,
	Benjamin Herrenschmidt, Logan Gunthorpe

[+cc Ben, Logan]

Ben, Logan, since you're looking at the resource code, maybe you'd be
interested in this as well?

On Wed, May 22, 2019 at 02:30:30PM +0000, Nicholas Johnson wrote:
> Rebase patches to apply cleanly to 5.2-rc1 source. Remove patch for 
> comment style cleanup as this has already been applied.

Thanks for rebasing these.

They do apply cleanly, but they seem to be base64-encoded MIME
attachments, and I don't know how to make mutt extract them easily.  I
had to save each patch attachment individually, apply it, insert the
commit log manually, etc.

Is there any chance you could send the next series as plain-text
patches?  That would be a lot easier for me.

> Anybody interested in testing, you can do so with:
> 
> a) Intel system with Thunderbolt 3 and native enumeration. The Gigabyte 
> Z390 Designare is one of the most perfect for this that I have never had 
> the opportunity to use - it does not even have the option for BIOS 
> assisted enumeration present in the BIOS.
> 
> b) Any system with PCIe and the Gigabyte GC-TITAN RIDGE add-in card, 
> jump the header as described and use kernel parameters like:
> 
> pci=assign-busses,hpbussize=0x33,realloc,hpmemsize=128M,hpmemprefsize=1G,nocrs 
> pcie_ports=native
> 
> [optional] pci.dyndbg
> 
>     ___
>  __/   \__
> |o o o o o| When looking into the receptacle on back of PCIe card.
> |_________| Jump pins 3 and 5.
> 
>  1 2 3 4 5
> 
> The Intel system is nice in that it should just work. The add-in card 
> setup is nice in that you can go nuts and assign copious amounts of 
> MMIO_PREF - can anybody show a Xeon Phi coprocessor with 16G BAR working 
> in an eGPU enclosure with these patches?
> 
> However, if you specify the above kernel parameters on the Intel system, 
> you should be able to override it to allocate more space.
> 
> Nicholas Johnson (4):
>   PCI: Consider alignment of hot-added bridges when distributing
>     available resources
>   PCI: Modify extend_bridge_window() to set resource size directly
>   PCI: Fix bug resulting in double hpmemsize being assigned to MMIO
>     window
>   PCI: Add pci=hpmemprefsize parameter to set MMIO_PREF size
>     independently
> 
>  .../admin-guide/kernel-parameters.txt         |   7 +-
>  drivers/pci/pci.c                             |  18 +-
>  drivers/pci/setup-bus.c                       | 265 ++++++++++--------
>  include/linux/pci.h                           |   3 +-
>  4 files changed, 167 insertions(+), 126 deletions(-)
> 
> -- 
> 2.20.1
> 

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v6 0/4] PCI: Patch series to support Thunderbolt without any BIOS support
  2019-06-15 19:56 ` Bjorn Helgaas
@ 2019-06-17 16:55   ` Logan Gunthorpe
  2019-07-01 14:33   ` Nicholas Johnson
  1 sibling, 0 replies; 4+ messages in thread
From: Logan Gunthorpe @ 2019-06-17 16:55 UTC (permalink / raw)
  To: Bjorn Helgaas, Nicholas Johnson
  Cc: linux-kernel, linux-pci, mika.westerberg, corbet, Benjamin Herrenschmidt



On 2019-06-15 1:56 p.m., Bjorn Helgaas wrote:
> [+cc Ben, Logan]
> 
> Ben, Logan, since you're looking at the resource code, maybe you'd be
> interested in this as well?
>
> On Wed, May 22, 2019 at 02:30:30PM +0000, Nicholas Johnson wrote:
>> Rebase patches to apply cleanly to 5.2-rc1 source. Remove patch for 
>> comment style cleanup as this has already been applied.
> 
> Thanks for rebasing these.
> 
> They do apply cleanly, but they seem to be base64-encoded MIME
> attachments, and I don't know how to make mutt extract them easily.  I
> had to save each patch attachment individually, apply it, insert the
> commit log manually, etc.
> 
> Is there any chance you could send the next series as plain-text
> patches?  That would be a lot easier for me.

I'd happily look at the patches but I can't find them. Sounds like they
were sent as attachments and it doesn't seem like the mailing list
archives keep those.

Logan



^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v6 0/4] PCI: Patch series to support Thunderbolt without any BIOS support
  2019-06-15 19:56 ` Bjorn Helgaas
  2019-06-17 16:55   ` Logan Gunthorpe
@ 2019-07-01 14:33   ` Nicholas Johnson
  1 sibling, 0 replies; 4+ messages in thread
From: Nicholas Johnson @ 2019-07-01 14:33 UTC (permalink / raw)
  To: Bjorn Helgaas
  Cc: linux-kernel, linux-pci, mika.westerberg, corbet,
	Benjamin Herrenschmidt, Logan Gunthorpe

On Sun, Jun 16, 2019 at 03:56:19AM +0800, Bjorn Helgaas wrote:
> [+cc Ben, Logan]
> 
> Ben, Logan, since you're looking at the resource code, maybe you'd be
> interested in this as well?
> 
> On Wed, May 22, 2019 at 02:30:30PM +0000, Nicholas Johnson wrote:
> > Rebase patches to apply cleanly to 5.2-rc1 source. Remove patch for 
> > comment style cleanup as this has already been applied.
> 
> Thanks for rebasing these.
> 
> They do apply cleanly, but they seem to be base64-encoded MIME
> attachments, and I don't know how to make mutt extract them easily.  I
> had to save each patch attachment individually, apply it, insert the
> commit log manually, etc.
> 
> Is there any chance you could send the next series as plain-text
> patches?  That would be a lot easier for me.
> 
> > Anybody interested in testing, you can do so with:
> > 
> > a) Intel system with Thunderbolt 3 and native enumeration. The Gigabyte 
> > Z390 Designare is one of the most perfect for this that I have never had 
> > the opportunity to use - it does not even have the option for BIOS 
> > assisted enumeration present in the BIOS.
> > 
> > b) Any system with PCIe and the Gigabyte GC-TITAN RIDGE add-in card, 
> > jump the header as described and use kernel parameters like:
> > 
> > pci=assign-busses,hpbussize=0x33,realloc,hpmemsize=128M,hpmemprefsize=1G,nocrs 
> > pcie_ports=native
> > 
> > [optional] pci.dyndbg
> > 
> >     ___
> >  __/   \__
> > |o o o o o| When looking into the receptacle on back of PCIe card.
> > |_________| Jump pins 3 and 5.
> > 
> >  1 2 3 4 5
> > 
> > The Intel system is nice in that it should just work. The add-in card 
> > setup is nice in that you can go nuts and assign copious amounts of 
> > MMIO_PREF - can anybody show a Xeon Phi coprocessor with 16G BAR working 
> > in an eGPU enclosure with these patches?
> > 
> > However, if you specify the above kernel parameters on the Intel system, 
> > you should be able to override it to allocate more space.
> > 
> > Nicholas Johnson (4):
> >   PCI: Consider alignment of hot-added bridges when distributing
> >     available resources
> >   PCI: Modify extend_bridge_window() to set resource size directly
> >   PCI: Fix bug resulting in double hpmemsize being assigned to MMIO
> >     window
> >   PCI: Add pci=hpmemprefsize parameter to set MMIO_PREF size
> >     independently
> > 
> >  .../admin-guide/kernel-parameters.txt         |   7 +-
> >  drivers/pci/pci.c                             |  18 +-
> >  drivers/pci/setup-bus.c                       | 265 ++++++++++--------
> >  include/linux/pci.h                           |   3 +-
> >  4 files changed, 167 insertions(+), 126 deletions(-)
> > 
> > -- 
> > 2.20.1
> > 
I posted PATCH v7, finally. I needed a place to announce that the 
patches 1-2/8 which were made by Bjorn would not send with him as the 
"from" which seems to attribute the author.

Credits go to Bjorn for PATCH v7 1-2/8 (the first two patches) but to
send them I had to put myself in that field.

When applying them, I guess you will have to modify that field, Bjorn. 
My apologies if there was a way around it.

Thanks for all the comments and feedback from everybody.

^ permalink raw reply	[flat|nested] 4+ messages in thread

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Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2019-05-22 14:30 [PATCH v6 0/4] PCI: Patch series to support Thunderbolt without any BIOS support Nicholas Johnson
2019-06-15 19:56 ` Bjorn Helgaas
2019-06-17 16:55   ` Logan Gunthorpe
2019-07-01 14:33   ` Nicholas Johnson

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