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Mon, 19 Aug 2019 19:30:52 +0000 From: Haiyang Zhang To: "sashal@kernel.org" , "davem@davemloft.net" , "saeedm@mellanox.com" , "leon@kernel.org" , "eranbe@mellanox.com" , "lorenzo.pieralisi@arm.com" , "bhelgaas@google.com" , "linux-pci@vger.kernel.org" , "linux-hyperv@vger.kernel.org" , "netdev@vger.kernel.org" CC: Haiyang Zhang , KY Srinivasan , Stephen Hemminger , "linux-kernel@vger.kernel.org" Subject: [PATCH net-next,v2 3/6] net/mlx5: Add wrappers for HyperV PCIe operations Thread-Topic: [PATCH net-next,v2 3/6] net/mlx5: Add wrappers for HyperV PCIe operations Thread-Index: AQHVVsSdJ36dPGYgDEegIU5DCBZYUw== Date: Mon, 19 Aug 2019 19:30:52 +0000 Message-ID: <1566242976-108801-4-git-send-email-haiyangz@microsoft.com> References: <1566242976-108801-1-git-send-email-haiyangz@microsoft.com> In-Reply-To: <1566242976-108801-1-git-send-email-haiyangz@microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MWHPR12CA0059.namprd12.prod.outlook.com (2603:10b6:300:103::21) To DM6PR21MB1242.namprd21.prod.outlook.com (2603:10b6:5:169::22) authentication-results: spf=none (sender IP is ) smtp.mailfrom=lkmlhyz@microsoft.com; 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received-spf: None (protection.outlook.com: microsoft.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 5/ZubkahAYktCzVv/CB7Gt9MAf0Kz2aW3Aq8sYI4mMAq6u38QTSx+k+7ShGKjwy5FL9dzD3rJDTXNkImeow9jVKOxyPwI2WbSjDD8sYpv52YZOKCDX3/F4SpsSrxlgpinWRRpx0iHvRGsHqfKduui5RoXpXSdahpFoB+TMLPEH6ZTwrWLAwQDhrQG1/TSZ1Gq43iDcGj/Yty+SrcNlgYXNOjyfnkXbUB8WThfjtgst0YZ+KbR1tJ5r+/vbrqs7p9wd+hMlhYZFdGOTpxm3A4LRrjzkP4742Gu7KT7moA8gCxQAsoyfJhecN4cWPuWoAITJFv6HeyR8uYiIetmulY19qTIz/nQDWHTvVOfzhBgRSiMGaP578gihh26ENWcqj2RJGYf1AgM9tJ4F6Z5fH9VuHPwFgdKahHxCypKLuaLOM= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: b22b323f-8fc4-4f52-4c99-08d724dbbf86 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Aug 2019 19:30:52.7151 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: YLmMh6VOp/ZysTQhWHYu46FHBF8yk8OOnc4CykWFUJaB8oFvkz0eUttvfNvQQ+dL58H9ZnKTNLrikiGJE5rwSA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR21MB1145 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Eran Ben Elisha Add wrapper functions for HyperV PCIe read / write / block_invalidate_register operations. This will be used as an infrastructure in the downstream patch for software communication. This will be enabled by default if CONFIG_PCI_HYPERV_INTERFACE is set. Signed-off-by: Eran Ben Elisha Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/Makefile | 1 + drivers/net/ethernet/mellanox/mlx5/core/lib/hv.c | 64 ++++++++++++++++++++= ++++ drivers/net/ethernet/mellanox/mlx5/core/lib/hv.h | 22 ++++++++ 3 files changed, 87 insertions(+) create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/lib/hv.c create mode 100644 drivers/net/ethernet/mellanox/mlx5/core/lib/hv.h diff --git a/drivers/net/ethernet/mellanox/mlx5/core/Makefile b/drivers/net= /ethernet/mellanox/mlx5/core/Makefile index 8b7edaa..247295b 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/Makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/Makefile @@ -45,6 +45,7 @@ mlx5_core-$(CONFIG_MLX5_ESWITCH) +=3D eswitch.o eswitch= _offloads.o eswitch_offlo mlx5_core-$(CONFIG_MLX5_MPFS) +=3D lib/mpfs.o mlx5_core-$(CONFIG_VXLAN) +=3D lib/vxlan.o mlx5_core-$(CONFIG_PTP_1588_CLOCK) +=3D lib/clock.o +mlx5_core-$(CONFIG_PCI_HYPERV_INTERFACE) +=3D lib/hv.o =20 # # Ipoib netdev diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/hv.c b/drivers/net= /ethernet/mellanox/mlx5/core/lib/hv.c new file mode 100644 index 0000000..cf08d02 --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/hv.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB +// Copyright (c) 2018 Mellanox Technologies + +#include +#include "mlx5_core.h" +#include "lib/hv.h" + +static int mlx5_hv_config_common(struct mlx5_core_dev *dev, void *buf, int= len, + int offset, bool read) +{ + int rc =3D -EOPNOTSUPP; + int bytes_returned; + int block_id; + + if (offset % HV_CONFIG_BLOCK_SIZE_MAX || len % HV_CONFIG_BLOCK_SIZE_MAX) + return -EINVAL; + + block_id =3D offset / HV_CONFIG_BLOCK_SIZE_MAX; + + rc =3D read ? + hyperv_read_cfg_blk(dev->pdev, buf, + HV_CONFIG_BLOCK_SIZE_MAX, block_id, + &bytes_returned) : + hyperv_write_cfg_blk(dev->pdev, buf, + HV_CONFIG_BLOCK_SIZE_MAX, block_id); + + /* Make sure len bytes were read successfully */ + if (read) + rc |=3D !(len =3D=3D bytes_returned); + + if (rc) { + mlx5_core_err(dev, "Failed to %s hv config, err =3D %d, len =3D %d, offs= et =3D %d\n", + read ? "read" : "write", rc, len, + offset); + return rc; + } + + return 0; +} + +int mlx5_hv_read_config(struct mlx5_core_dev *dev, void *buf, int len, + int offset) +{ + return mlx5_hv_config_common(dev, buf, len, offset, true); +} + +int mlx5_hv_write_config(struct mlx5_core_dev *dev, void *buf, int len, + int offset) +{ + return mlx5_hv_config_common(dev, buf, len, offset, false); +} + +int mlx5_hv_register_invalidate(struct mlx5_core_dev *dev, void *context, + void (*block_invalidate)(void *context, + u64 block_mask)) +{ + return hyperv_reg_block_invalidate(dev->pdev, context, + block_invalidate); +} + +void mlx5_hv_unregister_invalidate(struct mlx5_core_dev *dev) +{ + hyperv_reg_block_invalidate(dev->pdev, NULL, NULL); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/hv.h b/drivers/net= /ethernet/mellanox/mlx5/core/lib/hv.h new file mode 100644 index 0000000..f9a4557 --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/hv.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ +/* Copyright (c) 2019 Mellanox Technologies. */ + +#ifndef __LIB_HV_H__ +#define __LIB_HV_H__ + +#if IS_ENABLED(CONFIG_PCI_HYPERV_INTERFACE) + +#include +#include + +int mlx5_hv_read_config(struct mlx5_core_dev *dev, void *buf, int len, + int offset); +int mlx5_hv_write_config(struct mlx5_core_dev *dev, void *buf, int len, + int offset); +int mlx5_hv_register_invalidate(struct mlx5_core_dev *dev, void *context, + void (*block_invalidate)(void *context, + u64 block_mask)); +void mlx5_hv_unregister_invalidate(struct mlx5_core_dev *dev); +#endif + +#endif /* __LIB_HV_H__ */ --=20 1.8.3.1