From: Anvesh Salveru <anvesh.s@samsung.com>
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: bhelgaas@google.com, gustavo.pimentel@synopsys.com,
jingoohan1@gmail.com, pankaj.dubey@samsung.com,
Anvesh Salveru <anvesh.s@samsung.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Andrew Murray <andrew.murray@arm.com>
Subject: [PATCH v2 2/2] PCI: dwc: Add support to handle ZRX-DC Compliant PHYs
Date: Mon, 28 Oct 2019 17:46:28 +0530 [thread overview]
Message-ID: <1572264988-17455-3-git-send-email-anvesh.s@samsung.com> (raw)
In-Reply-To: <1572264988-17455-1-git-send-email-anvesh.s@samsung.com>
Many platforms use DesignWare controller but the PHY can be different in
different platforms. If the PHY is compliant to the ZRX-DC specification
it helps lower power consumption during power states.
If current data rate is 8.0 GT/s or higher and PHY is not compliant to
ZRX-DC specification, then after every 100ms link should transition to
recovery state during the low power states.
DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in
GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.
Platforms with ZRX-DC compliant PHY can set "snps,phy-zrxdc-compliant"
property in controller DT node to specify this property to the controller.
CC: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
CC: Andrew Murray <andrew.murray@arm.com>
Signed-off-by: Anvesh Salveru <anvesh.s@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change in v2:
- trivial change in patch description
drivers/pci/controller/dwc/pcie-designware.c | 7 +++++++
drivers/pci/controller/dwc/pcie-designware.h | 3 +++
2 files changed, 10 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 820488dfeaed..6560d9f765d7 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -556,4 +556,11 @@ void dw_pcie_setup(struct dw_pcie *pci)
PCIE_PL_CHK_REG_CHK_REG_START;
dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
}
+
+ if (of_property_read_bool(np, "snps,phy-zrxdc-compliant")) {
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED);
+ val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL;
+ dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val);
+ }
+
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 5a18e94e52c8..427a55ec43c6 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -60,6 +60,9 @@
#define PCIE_MSI_INTR0_MASK 0x82C
#define PCIE_MSI_INTR0_STATUS 0x830
+#define PCIE_PORT_GEN3_RELATED 0x890
+#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0)
+
#define PCIE_ATU_VIEWPORT 0x900
#define PCIE_ATU_REGION_INBOUND BIT(31)
#define PCIE_ATU_REGION_OUTBOUND 0
--
2.17.1
prev parent reply other threads:[~2019-10-28 12:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20191028121704epcas5p483bf05ccb4cd25b1757cd5645e819d12@epcas5p4.samsung.com>
2019-10-28 12:16 ` [PATCH v2 0/2] Add support to handle ZRX-DC Compliant PHYs Anvesh Salveru
[not found] ` <CGME20191028121748epcas5p3054c9583c14a2edde9f725d005895a04@epcas5p3.samsung.com>
2019-10-28 12:16 ` [PATCH v2 1/2] dt-bindings: PCI: designware: Add binding for ZRX-DC PHY property Anvesh Salveru
2019-11-05 21:53 ` Rob Herring
2019-11-06 9:53 ` Andrew Murray
2019-11-08 3:24 ` Pankaj Dubey
2019-11-08 9:55 ` Andrew Murray
2019-11-11 17:52 ` Rob Herring
[not found] ` <CGME20191028121758epcas5p2dda6d0842be32bcab2e6025fac1f3e78@epcas5p2.samsung.com>
2019-10-28 12:16 ` Anvesh Salveru [this message]
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