From: Shawn Lin <shawn.lin@rock-chips.com>
To: Heiko Stuebner <heiko@sntech.de>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jingoohan1@gmail.com>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
William Wu <william.wu@rock-chips.com>,
Simon Xue <xxm@rock-chips.com>,
linux-rockchip@lists.infradead.org,
Shawn Lin <shawn.lin@rock-chips.com>
Subject: [PATCH v2 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP
Date: Thu, 13 Feb 2020 14:08:06 +0800 [thread overview]
Message-ID: <1581574091-240890-2-git-send-email-shawn.lin@rock-chips.com> (raw)
In-Reply-To: <1581574091-240890-1-git-send-email-shawn.lin@rock-chips.com>
This IP could supports USB3.0 and PCIe.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2:
- fix yaml format
.../bindings/phy/rockchip,inno-combophy.yaml | 80 ++++++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml
diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml
new file mode 100644
index 0000000..841f88a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip,inno-combophy.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/rockchip,inno-combophy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip USB3.0/PCI-e combo phy
+
+maintainers:
+ - Shawn Lin <shawn.lin@rock-chips.com>
+ - William Wu <william.wu@rock-chips.com>
+
+properties:
+ "#phy-cells":
+ const: 1
+
+ compatible:
+ enum:
+ - rockchip,rk1808-combphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PLL reference clock
+
+ clock-names:
+ items:
+ - const: refclk
+
+ resets:
+ items:
+ - description: OTG unit reset line
+ - description: POR unit reset line
+ - description: APB interface reset line
+ - description: PIPE unit reset line
+
+ reset-names:
+ items:
+ - const: otg-rst
+ - const: combphy-por
+ - const: combphy-apb
+ - const: combphy-pipe
+
+ rockchip,combphygrf:
+ enum:
+ - rockchip,combphygrf
+ description: The grf for COMBPHY configuration and state registers.
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - rockchip,combphygrf
+
+additionalProperties: false
+
+examples:
+ - |
+ combphy: phy@ff380000 {
+ compatible = "rockchip,rk1808-combphy";
+ reg = <0x0 0xff380000 0x0 0x10000>;
+ #phy-cells = <1>;
+ clocks = <&cru SCLK_PCIEPHY_REF>;
+ clock-names = "refclk";
+ assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+ assigned-clock-rates = <25000000>;
+ resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>,
+ <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>;
+ reset-names = "otg-rst", "combphy-por",
+ "combphy-apb", "combphy-pipe";
+ rockchip,combphygrf = <&combphy_grf>;
+ };
+
+...
--
1.9.1
next prev parent reply other threads:[~2020-02-13 6:10 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-13 6:08 [PATCH v2 0/6] Add Rockchip new PCIe controller and combo phy support Shawn Lin
2020-02-13 6:08 ` Shawn Lin [this message]
2020-02-13 20:46 ` [PATCH v2 1/6] dt-bindings: add binding for Rockchip combo phy using an Innosilicon IP Rob Herring
2020-02-14 9:20 ` Heiko Stuebner
2020-02-13 6:08 ` [PATCH v2 2/6] phy/rockchip: inno-combophy: Add initial support Shawn Lin
2020-02-13 6:08 ` [PATCH v2 3/6] PCI: dwc: Skip allocating own MSI domain if using external MSI domain Shawn Lin
2020-05-07 14:00 ` Rob Herring
2020-02-13 6:08 ` [PATCH v2 4/6] dt-bindings: rockchip: Add DesignWare based PCIe controller Shawn Lin
2020-02-13 20:47 ` Rob Herring
2020-05-07 14:09 ` Rob Herring
2020-02-13 6:10 ` [PATCH v2 5/6] PCI: rockchip: add " Shawn Lin
2020-02-13 6:10 ` [PATCH v2 6/6] MAINTAINERS: Update PCIe drivers for Rockchip Shawn Lin
2020-05-07 15:36 ` [PATCH v2 5/6] PCI: rockchip: add DesignWare based PCIe controller Rob Herring
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