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From: Yicong Yang <>
To: <>, <>, <>
Cc: <>, <>
Subject: [PATCH] PCI/PM: Fix wrong field set when config L1SS
Date: Thu, 12 Mar 2020 19:23:11 +0800	[thread overview]
Message-ID: <> (raw)

We enable proper L1 substates in the end of pcie_config_aspm_l1ss(). It's
PCI_L1SS_CTL1_L1SS_MASK field should we set in PCI_L1SS_CTL1 register
rather than PCI_L1SS_CAP_L1_PM_SS.

Signed-off-by: Yicong Yang <>
 drivers/pci/pcie/aspm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index 0dcd443..c2596e7 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -747,9 +747,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
 	/* Enable what we need to enable */
 	pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1,
-				PCI_L1SS_CAP_L1_PM_SS, val);
+				PCI_L1SS_CTL1_L1SS_MASK, val);
 	pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1,
-				PCI_L1SS_CAP_L1_PM_SS, val);
+				PCI_L1SS_CTL1_L1SS_MASK, val);
 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)

             reply	other threads:[~2020-03-12 11:27 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-12 11:23 Yicong Yang [this message]
2020-03-12 19:42 ` [PATCH] PCI/PM: Fix wrong field set when config L1SS Bjorn Helgaas

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