From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Andrew Murray <andrew.murray@arm.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Masami Hiramatsu <masami.hiramatsu@linaro.org>,
Jassi Brar <jaswinder.singh@linaro.org>,
Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Subject: [PATCH v3 1/2] dt-bindings: PCI: Add UniPhier PCIe endpoint controller description
Date: Mon, 23 Mar 2020 18:40:53 +0900 [thread overview]
Message-ID: <1584956454-8829-2-git-send-email-hayashi.kunihiko@socionext.com> (raw)
In-Reply-To: <1584956454-8829-1-git-send-email-hayashi.kunihiko@socionext.com>
Add DT bindings for PCIe controller implemented in UniPhier SoCs
when configured in endpoint mode. This controller is based on
the DesignWare PCIe core.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/pci/uniphier-pcie-ep.txt | 53 ++++++++++++++++++++++
MAINTAINERS | 2 +-
2 files changed, 54 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/pci/uniphier-pcie-ep.txt
diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie-ep.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie-ep.txt
new file mode 100644
index 0000000..072dc78
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/uniphier-pcie-ep.txt
@@ -0,0 +1,53 @@
+Socionext UniPhier PCIe endpoint controller bindings
+
+This describes the devicetree bindings for PCIe endpoint controller
+implemented on Socionext UniPhier SoCs.
+
+UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
+PCI core. It shares common functions with the PCIe DesignWare core driver
+and inherits common properties defined in
+Documentation/devicetree/bindings/pci/designware-pcie.txt.
+
+Required properties:
+- compatible: Should be
+ "socionext,uniphier-pro5-pcie-ep" for Pro5 SoC
+- reg: Specifies offset and length of the register set for the device.
+ According to the reg-names, appropriate register sets are required.
+- reg-names: Must include the following entries:
+ "dbi" - controller configuration registers
+ "dbi2" - controller configuration registers for shadow
+ "link" - SoC-specific glue layer registers
+ "addr_space" - PCIe configuration space
+- clocks: A phandle to the clock gate for PCIe glue layer including
+ the endpoint controller.
+- clock-names: Should contain the following:
+ "gio", "link" - for Pro5 SoC
+- resets: A phandle to the reset line for PCIe glue layer including
+ the endpoint controller.
+- reset-names: Should contain the following:
+ "gio", "link" - for Pro5 SoC
+
+Optional properties:
+- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate
+ phys are required.
+- phy-names: Must be "pcie-phy".
+
+Example:
+
+ pcie_ep: pcie-ep@66000000 {
+ compatible = "socionext,uniphier-pro5-pcie-ep",
+ "snps,dw-pcie-ep";
+ status = "disabled";
+ reg-names = "dbi", "dbi2", "link", "addr_space";
+ reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
+ <0x66010000 0x10000>, <0x67000000 0x400000>;
+ clock-names = "gio", "link";
+ clocks = <&sys_clk 12>, <&sys_clk 24>;
+ reset-names = "gio", "link";
+ clocks = <&sys_rst 12>, <&sys_rst 24>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ num-lanes = <4>;
+ phy-names = "pcie-phy";
+ phys = <&pcie_phy>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 50e8b90..01a4631 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13151,7 +13151,7 @@ PCIE DRIVER FOR SOCIONEXT UNIPHIER
M: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
L: linux-pci@vger.kernel.org
S: Maintained
-F: Documentation/devicetree/bindings/pci/uniphier-pcie.txt
+F: Documentation/devicetree/bindings/pci/uniphier-pcie*.txt
F: drivers/pci/controller/dwc/pcie-uniphier.c
PCIE DRIVER FOR ST SPEAR13XX
--
2.7.4
next prev parent reply other threads:[~2020-03-23 9:41 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-23 9:40 [PATCH v3 0/2] PCI: Add new UniPhier PCIe endpoint driver Kunihiko Hayashi
2020-03-23 9:40 ` Kunihiko Hayashi [this message]
2020-05-08 8:39 ` [PATCH v3 1/2] dt-bindings: PCI: Add UniPhier PCIe endpoint controller description Kunihiko Hayashi
2020-03-23 9:40 ` [PATCH v3 2/2] PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver Kunihiko Hayashi
2020-05-07 19:33 ` Rob Herring
2020-05-08 8:32 ` Kunihiko Hayashi
2020-04-22 5:13 ` [PATCH v3 0/2] PCI: Add new UniPhier PCIe endpoint driver Kunihiko Hayashi
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