From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94CE5C4332E for ; Mon, 23 Mar 2020 09:41:10 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7434A20769 for ; Mon, 23 Mar 2020 09:41:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727772AbgCWJlG (ORCPT ); Mon, 23 Mar 2020 05:41:06 -0400 Received: from mx.socionext.com ([202.248.49.38]:5868 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727758AbgCWJlF (ORCPT ); Mon, 23 Mar 2020 05:41:05 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 23 Mar 2020 18:41:03 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 9461960057; Mon, 23 Mar 2020 18:41:03 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Mon, 23 Mar 2020 18:41:03 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 13AED1A12AD; Mon, 23 Mar 2020 18:41:03 +0900 (JST) From: Kunihiko Hayashi To: Bjorn Helgaas , Lorenzo Pieralisi , Andrew Murray , Masahiro Yamada , Rob Herring , Mark Rutland Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v3 1/2] dt-bindings: PCI: Add UniPhier PCIe endpoint controller description Date: Mon, 23 Mar 2020 18:40:53 +0900 Message-Id: <1584956454-8829-2-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584956454-8829-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1584956454-8829-1-git-send-email-hayashi.kunihiko@socionext.com> Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Add DT bindings for PCIe controller implemented in UniPhier SoCs when configured in endpoint mode. This controller is based on the DesignWare PCIe core. Signed-off-by: Kunihiko Hayashi Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/uniphier-pcie-ep.txt | 53 ++++++++++++++++++++++ MAINTAINERS | 2 +- 2 files changed, 54 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/pci/uniphier-pcie-ep.txt diff --git a/Documentation/devicetree/bindings/pci/uniphier-pcie-ep.txt b/Documentation/devicetree/bindings/pci/uniphier-pcie-ep.txt new file mode 100644 index 0000000..072dc78 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/uniphier-pcie-ep.txt @@ -0,0 +1,53 @@ +Socionext UniPhier PCIe endpoint controller bindings + +This describes the devicetree bindings for PCIe endpoint controller +implemented on Socionext UniPhier SoCs. + +UniPhier PCIe endpoint controller is based on the Synopsys DesignWare +PCI core. It shares common functions with the PCIe DesignWare core driver +and inherits common properties defined in +Documentation/devicetree/bindings/pci/designware-pcie.txt. + +Required properties: +- compatible: Should be + "socionext,uniphier-pro5-pcie-ep" for Pro5 SoC +- reg: Specifies offset and length of the register set for the device. + According to the reg-names, appropriate register sets are required. +- reg-names: Must include the following entries: + "dbi" - controller configuration registers + "dbi2" - controller configuration registers for shadow + "link" - SoC-specific glue layer registers + "addr_space" - PCIe configuration space +- clocks: A phandle to the clock gate for PCIe glue layer including + the endpoint controller. +- clock-names: Should contain the following: + "gio", "link" - for Pro5 SoC +- resets: A phandle to the reset line for PCIe glue layer including + the endpoint controller. +- reset-names: Should contain the following: + "gio", "link" - for Pro5 SoC + +Optional properties: +- phys: A phandle to generic PCIe PHY. According to the phy-names, appropriate + phys are required. +- phy-names: Must be "pcie-phy". + +Example: + + pcie_ep: pcie-ep@66000000 { + compatible = "socionext,uniphier-pro5-pcie-ep", + "snps,dw-pcie-ep"; + status = "disabled"; + reg-names = "dbi", "dbi2", "link", "addr_space"; + reg = <0x66000000 0x1000>, <0x66001000 0x1000>, + <0x66010000 0x10000>, <0x67000000 0x400000>; + clock-names = "gio", "link"; + clocks = <&sys_clk 12>, <&sys_clk 24>; + reset-names = "gio", "link"; + clocks = <&sys_rst 12>, <&sys_rst 24>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-lanes = <4>; + phy-names = "pcie-phy"; + phys = <&pcie_phy>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 50e8b90..01a4631 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13151,7 +13151,7 @@ PCIE DRIVER FOR SOCIONEXT UNIPHIER M: Kunihiko Hayashi L: linux-pci@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/pci/uniphier-pcie.txt +F: Documentation/devicetree/bindings/pci/uniphier-pcie*.txt F: drivers/pci/controller/dwc/pcie-uniphier.c PCIE DRIVER FOR ST SPEAR13XX -- 2.7.4