* [PATCH v7 1/3] PCI: portdrv: Add pcie_port_service_get_irq() function
2020-09-11 9:33 [PATCH v7 0/3] PCI: uniphier: Add PME/AER support for UniPhier PCIe host controller Kunihiko Hayashi
@ 2020-09-11 9:33 ` Kunihiko Hayashi
2020-10-07 16:42 ` Rob Herring
2020-09-11 9:33 ` [PATCH v7 2/3] PCI: dwc: Add msi_host_isr() callback Kunihiko Hayashi
` (2 subsequent siblings)
3 siblings, 1 reply; 7+ messages in thread
From: Kunihiko Hayashi @ 2020-09-11 9:33 UTC (permalink / raw)
To: Bjorn Helgaas, Lorenzo Pieralisi, Jingoo Han, Gustavo Pimentel,
Rob Herring, Marc Zyngier
Cc: linux-pci, linux-arm-kernel, linux-kernel, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
Add pcie_port_service_get_irq() that returns the virtual IRQ number
for specified portdrv service.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/pci/pcie/portdrv.h | 1 +
drivers/pci/pcie/portdrv_core.c | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h
index af7cf23..e256456 100644
--- a/drivers/pci/pcie/portdrv.h
+++ b/drivers/pci/pcie/portdrv.h
@@ -150,4 +150,5 @@ static inline void pcie_pme_interrupt_enable(struct pci_dev *dev, bool en) {}
#endif /* !CONFIG_PCIE_PME */
struct device *pcie_port_find_device(struct pci_dev *dev, u32 service);
+int pcie_port_service_get_irq(struct pci_dev *dev, u32 service);
#endif /* _PORTDRV_H_ */
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 50a9522..f92daf8 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -480,6 +480,22 @@ struct device *pcie_port_find_device(struct pci_dev *dev,
}
EXPORT_SYMBOL_GPL(pcie_port_find_device);
+/*
+ * pcie_port_service_get_irq - get irq of the service
+ * @dev: PCI Express port the service is associated with
+ * @service: For the service to find
+ *
+ * Get irq number associated with given service on a pci_dev
+ */
+int pcie_port_service_get_irq(struct pci_dev *dev, u32 service)
+{
+ struct pcie_device *pciedev;
+
+ pciedev = to_pcie_device(pcie_port_find_device(dev, service));
+
+ return pciedev->irq;
+}
+
/**
* pcie_port_device_remove - unregister PCI Express port service devices
* @dev: PCI Express port the service devices to unregister are associated with
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v7 2/3] PCI: dwc: Add msi_host_isr() callback
2020-09-11 9:33 [PATCH v7 0/3] PCI: uniphier: Add PME/AER support for UniPhier PCIe host controller Kunihiko Hayashi
2020-09-11 9:33 ` [PATCH v7 1/3] PCI: portdrv: Add pcie_port_service_get_irq() function Kunihiko Hayashi
@ 2020-09-11 9:33 ` Kunihiko Hayashi
2020-09-11 9:33 ` [PATCH v7 3/3] PCI: uniphier: Add misc interrupt handler to invoke PME and AER Kunihiko Hayashi
2020-10-07 4:23 ` [PATCH v7 0/3] PCI: uniphier: Add PME/AER support for UniPhier PCIe host controller Kunihiko Hayashi
3 siblings, 0 replies; 7+ messages in thread
From: Kunihiko Hayashi @ 2020-09-11 9:33 UTC (permalink / raw)
To: Bjorn Helgaas, Lorenzo Pieralisi, Jingoo Han, Gustavo Pimentel,
Rob Herring, Marc Zyngier
Cc: linux-pci, linux-arm-kernel, linux-kernel, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
This adds msi_host_isr() callback function support to describe
SoC-dependent service triggered by MSI.
For example, when AER interrupt is triggered by MSI, the callback function
reads SoC-dependent registers and detects that the interrupt is from AER,
and invoke AER interrupts related to MSI.
Cc: Marc Zyngier <maz@kernel.org>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 317ff51..f211510 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -61,6 +61,9 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
irqreturn_t ret = IRQ_NONE;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ if (pp->ops->msi_host_isr)
+ pp->ops->msi_host_isr(pp);
+
num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
for (i = 0; i < num_ctrls; i++) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 8cbc902..68feb91 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -171,6 +171,7 @@ struct dw_pcie_host_ops {
int (*host_init)(struct pcie_port *pp);
void (*set_num_vectors)(struct pcie_port *pp);
int (*msi_host_init)(struct pcie_port *pp);
+ void (*msi_host_isr)(struct pcie_port *pp);
};
struct pcie_port {
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v7 3/3] PCI: uniphier: Add misc interrupt handler to invoke PME and AER
2020-09-11 9:33 [PATCH v7 0/3] PCI: uniphier: Add PME/AER support for UniPhier PCIe host controller Kunihiko Hayashi
2020-09-11 9:33 ` [PATCH v7 1/3] PCI: portdrv: Add pcie_port_service_get_irq() function Kunihiko Hayashi
2020-09-11 9:33 ` [PATCH v7 2/3] PCI: dwc: Add msi_host_isr() callback Kunihiko Hayashi
@ 2020-09-11 9:33 ` Kunihiko Hayashi
2020-10-07 16:45 ` Rob Herring
2020-10-07 4:23 ` [PATCH v7 0/3] PCI: uniphier: Add PME/AER support for UniPhier PCIe host controller Kunihiko Hayashi
3 siblings, 1 reply; 7+ messages in thread
From: Kunihiko Hayashi @ 2020-09-11 9:33 UTC (permalink / raw)
To: Bjorn Helgaas, Lorenzo Pieralisi, Jingoo Han, Gustavo Pimentel,
Rob Herring, Marc Zyngier
Cc: linux-pci, linux-arm-kernel, linux-kernel, Masami Hiramatsu,
Jassi Brar, Kunihiko Hayashi
This patch adds misc interrupt handler to detect and invoke PME/AER event.
In UniPhier PCIe controller, PME/AER signals are assigned to the same
signal as MSI by the internal logic. These signals should be detected by
the internal register, however, DWC MSI handler can't handle these signals.
DWC MSI handler calls .msi_host_isr() callback function, that detects
PME/AER signals with the internal register and invokes the interrupt
with PME/AER vIRQ numbers.
These vIRQ numbers is obtained from portdrv in uniphier_add_pcie_port()
function.
Cc: Marc Zyngier <maz@kernel.org>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
drivers/pci/controller/dwc/pcie-uniphier.c | 77 +++++++++++++++++++++++++-----
1 file changed, 66 insertions(+), 11 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
index 4817626..237537a 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -21,6 +21,7 @@
#include <linux/reset.h>
#include "pcie-designware.h"
+#include "../../pcie/portdrv.h"
#define PCL_PINCTRL0 0x002c
#define PCL_PERST_PLDN_REGEN BIT(12)
@@ -44,7 +45,9 @@
#define PCL_SYS_AUX_PWR_DET BIT(8)
#define PCL_RCV_INT 0x8108
+#define PCL_RCV_INT_ALL_INT_MASK GENMASK(28, 25)
#define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17)
+#define PCL_RCV_INT_ALL_MSI_MASK GENMASK(12, 9)
#define PCL_CFG_BW_MGT_STATUS BIT(4)
#define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3)
#define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2)
@@ -68,6 +71,8 @@ struct uniphier_pcie_priv {
struct reset_control *rst;
struct phy *phy;
struct irq_domain *legacy_irq_domain;
+ int aer_irq;
+ int pme_irq;
};
#define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
@@ -167,7 +172,15 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci)
static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv)
{
- writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT);
+ u32 val;
+
+ val = PCL_RCV_INT_ALL_ENABLE;
+ if (pci_msi_enabled())
+ val |= PCL_RCV_INT_ALL_INT_MASK;
+ else
+ val |= PCL_RCV_INT_ALL_MSI_MASK;
+
+ writel(val, priv->base + PCL_RCV_INT);
writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX);
}
@@ -231,28 +244,52 @@ static const struct irq_domain_ops uniphier_intx_domain_ops = {
.map = uniphier_pcie_intx_map,
};
-static void uniphier_pcie_irq_handler(struct irq_desc *desc)
+static void uniphier_pcie_misc_isr(struct pcie_port *pp, bool is_msi)
{
- struct pcie_port *pp = irq_desc_get_handler_data(desc);
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
- struct irq_chip *chip = irq_desc_get_chip(desc);
- unsigned long reg;
- u32 val, bit, virq;
+ u32 val;
- /* INT for debug */
val = readl(priv->base + PCL_RCV_INT);
if (val & PCL_CFG_BW_MGT_STATUS)
dev_dbg(pci->dev, "Link Bandwidth Management Event\n");
+
if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n");
- if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
- dev_dbg(pci->dev, "Root Error\n");
- if (val & PCL_CFG_PME_MSI_STATUS)
- dev_dbg(pci->dev, "PME Interrupt\n");
+
+ if (is_msi) {
+ if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) {
+ dev_dbg(pci->dev, "Root Error Status\n");
+ if (priv->aer_irq)
+ generic_handle_irq(priv->aer_irq);
+ }
+
+ if (val & PCL_CFG_PME_MSI_STATUS) {
+ dev_dbg(pci->dev, "PME Interrupt\n");
+ if (priv->pme_irq)
+ generic_handle_irq(priv->pme_irq);
+ }
+ }
writel(val, priv->base + PCL_RCV_INT);
+}
+
+static void uniphier_pcie_msi_host_isr(struct pcie_port *pp)
+{
+ uniphier_pcie_misc_isr(pp, true);
+}
+
+static void uniphier_pcie_irq_handler(struct irq_desc *desc)
+{
+ struct pcie_port *pp = irq_desc_get_handler_data(desc);
+ struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned long reg;
+ u32 val, bit, virq;
+
+ uniphier_pcie_misc_isr(pp, false);
/* INTx */
chained_irq_enter(chip, desc);
@@ -329,6 +366,7 @@ static int uniphier_pcie_host_init(struct pcie_port *pp)
static const struct dw_pcie_host_ops uniphier_pcie_host_ops = {
.host_init = uniphier_pcie_host_init,
+ .msi_host_isr = uniphier_pcie_msi_host_isr,
};
static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv,
@@ -337,6 +375,7 @@ static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv,
struct dw_pcie *pci = &priv->pci;
struct pcie_port *pp = &pci->pp;
struct device *dev = &pdev->dev;
+ struct pci_dev *pcidev;
int ret;
pp->ops = &uniphier_pcie_host_ops;
@@ -353,6 +392,22 @@ static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv,
return ret;
}
+ /* irq for PME */
+ list_for_each_entry(pcidev, &pp->bridge->bus->devices, bus_list) {
+ priv->pme_irq =
+ pcie_port_service_get_irq(pcidev, PCIE_PORT_SERVICE_PME);
+ if (priv->pme_irq)
+ break;
+ }
+
+ /* irq for AER */
+ list_for_each_entry(pcidev, &pp->bridge->bus->devices, bus_list) {
+ priv->aer_irq =
+ pcie_port_service_get_irq(pcidev, PCIE_PORT_SERVICE_AER);
+ if (priv->aer_irq)
+ break;
+ }
+
return 0;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v7 0/3] PCI: uniphier: Add PME/AER support for UniPhier PCIe host controller
2020-09-11 9:33 [PATCH v7 0/3] PCI: uniphier: Add PME/AER support for UniPhier PCIe host controller Kunihiko Hayashi
` (2 preceding siblings ...)
2020-09-11 9:33 ` [PATCH v7 3/3] PCI: uniphier: Add misc interrupt handler to invoke PME and AER Kunihiko Hayashi
@ 2020-10-07 4:23 ` Kunihiko Hayashi
3 siblings, 0 replies; 7+ messages in thread
From: Kunihiko Hayashi @ 2020-10-07 4:23 UTC (permalink / raw)
To: Bjorn Helgaas, Lorenzo Pieralisi, Jingoo Han, Gustavo Pimentel,
Rob Herring, Marc Zyngier
Cc: linux-pci, linux-arm-kernel, linux-kernel, Masami Hiramatsu, Jassi Brar
Hi,
Gentle ping.
Are there any comments about this series?
Thank you,
On 2020/09/11 18:33, Kunihiko Hayashi wrote:
> The original subject up to v6 is
> "PCI: uniphier: Add features for UniPhier PCIe host controller".
>
> This adds a new function called by MSI handler in DesignWare PCIe framework,
> that invokes PME and AER funcions to detect the factor from SoC-dependent
> registers.
>
> The iATU patches is split from this series as
> "PCI: dwc: Move iATU register mapping to common framework".
>
> Changes since v6:
> - Separate patches for iATU and phy error from this series
> - Add Reviewed-by: line
>
> Changes since v5:
> - Add pcie_port_service_get_irq() function to pcie/portdrv
> - Call pcie_port_service_get_irq() to get vIRQ interrupt number for PME/AER
> - Rebase to the latest linux-next branch,
> and remove devm_platform_ioremap_resource_byname() replacement patch
>
> Changes since v4:
> - Add Acked-by: line to dwc patch
>
> Changes since v3:
> - Move msi_host_isr() call into dw_handle_msi_irq()
> - Move uniphier_pcie_misc_isr() call into the guard of chained_irq
> - Use a bool argument is_msi instead of pci_msi_enabled()
> - Consolidate handler calls for the same interrupt
> - Fix typos in commit messages
>
> Changes since v2:
> - Avoid printing phy error message in case of EPROBE_DEFER
> - Fix iATU register mapping method
> - dt-bindings: Add Acked-by: line
> - Fix typos in commit messages
> - Use devm_platform_ioremap_resource_byname()
>
> Changes since v1:
> - Add check if struct resource is NULL
> - Fix warning in the type of dev_err() argument
>
> Kunihiko Hayashi (3):
> PCI: portdrv: Add pcie_port_service_get_irq() function
> PCI: dwc: Add msi_host_isr() callback
> PCI: uniphier: Add misc interrupt handler to invoke PME and AER
>
> drivers/pci/controller/dwc/pcie-designware-host.c | 3 +
> drivers/pci/controller/dwc/pcie-designware.h | 1 +
> drivers/pci/controller/dwc/pcie-uniphier.c | 77 +++++++++++++++++++----
> drivers/pci/pcie/portdrv.h | 1 +
> drivers/pci/pcie/portdrv_core.c | 16 +++++
> 5 files changed, 87 insertions(+), 11 deletions(-)
>
--
---
Best Regards
Kunihiko Hayashi
^ permalink raw reply [flat|nested] 7+ messages in thread