linux-pci.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Megha Dey <megha.dey@intel.com>
To: tglx@linutronix.de
Cc: linux-kernel@vger.kernel.org, dave.jiang@intel.com,
	ashok.raj@intel.com, kevin.tian@intel.com, dwmw@amazon.co.uk,
	x86@kernel.org, tony.luck@intel.com, dan.j.williams@intel.com,
	megha.dey@intel.com, jgg@mellanox.com, kvm@vger.kernel.org,
	iommu@lists.linux-foundation.org, alex.williamson@redhat.com,
	bhelgaas@google.com, maz@kernel.org, linux-pci@vger.kernel.org,
	baolu.lu@linux.intel.com, ravi.v.shankar@intel.com,
	Joerg Roedel <joro@8bytes.org>
Subject: [Patch V2 10/13] iommu: Add capability IOMMU_CAP_VIOMMU_HINT
Date: Fri, 26 Feb 2021 12:11:14 -0800	[thread overview]
Message-ID: <1614370277-23235-11-git-send-email-megha.dey@intel.com> (raw)
In-Reply-To: <1614370277-23235-1-git-send-email-megha.dey@intel.com>

From: Lu Baolu <baolu.lu@linux.intel.com>

Some IOMMU specification defines some kind of hint mechanism, through
which BIOS can imply that OS runs in a virtualized environment. For
example, the caching mode defined in VT-d spec and NpCache capability
defined in the AMD IOMMU specification. This hint could also be used
outside of the IOMMU subsystem, where it could be used with other known
means (CPUID, smbios) to sense whether Linux is running in a virtualized
environment. Add a capability bit so that it could be used there.

Cc: Joerg Roedel <joro@8bytes.org>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Megha Dey <megha.dey@intel.com>
---
 drivers/iommu/amd/iommu.c    | 2 ++
 drivers/iommu/intel/iommu.c  | 5 +++++
 drivers/iommu/virtio-iommu.c | 9 +++++++++
 include/linux/iommu.h        | 2 ++
 4 files changed, 18 insertions(+)

diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index a69a8b5..a912318 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2140,6 +2140,8 @@ static bool amd_iommu_capable(enum iommu_cap cap)
 		return (irq_remapping_enabled == 1);
 	case IOMMU_CAP_NOEXEC:
 		return false;
+	case IOMMU_CAP_VIOMMU_HINT:
+		return amd_iommu_np_cache;
 	default:
 		break;
 	}
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index ee09323..55fa198 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -294,6 +294,7 @@ static inline void context_clear_entry(struct context_entry *context)
  */
 static struct dmar_domain *si_domain;
 static int hw_pass_through = 1;
+static int intel_caching_mode;
 
 #define for_each_domain_iommu(idx, domain)			\
 	for (idx = 0; idx < g_num_of_iommus; idx++)		\
@@ -3253,6 +3254,8 @@ static int __init init_dmars(void)
 
 		if (!ecap_pass_through(iommu->ecap))
 			hw_pass_through = 0;
+		if (cap_caching_mode(iommu->cap))
+			intel_caching_mode = 1;
 		intel_svm_check(iommu);
 	}
 
@@ -5113,6 +5116,8 @@ static bool intel_iommu_capable(enum iommu_cap cap)
 		return domain_update_iommu_snooping(NULL) == 1;
 	if (cap == IOMMU_CAP_INTR_REMAP)
 		return irq_remapping_enabled == 1;
+	if (cap == IOMMU_CAP_VIOMMU_HINT)
+		return intel_caching_mode;
 
 	return false;
 }
diff --git a/drivers/iommu/virtio-iommu.c b/drivers/iommu/virtio-iommu.c
index 2bfdd57..e4941ca 100644
--- a/drivers/iommu/virtio-iommu.c
+++ b/drivers/iommu/virtio-iommu.c
@@ -931,7 +931,16 @@ static int viommu_of_xlate(struct device *dev, struct of_phandle_args *args)
 	return iommu_fwspec_add_ids(dev, args->args, 1);
 }
 
+static bool viommu_capable(enum iommu_cap cap)
+{
+	if (cap == IOMMU_CAP_VIOMMU_HINT)
+		return true;
+
+	return false;
+}
+
 static struct iommu_ops viommu_ops = {
+	.capable		= viommu_capable,
 	.domain_alloc		= viommu_domain_alloc,
 	.domain_free		= viommu_domain_free,
 	.attach_dev		= viommu_attach_dev,
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 5e7fe51..9d0ade4 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -94,6 +94,8 @@ enum iommu_cap {
 					   transactions */
 	IOMMU_CAP_INTR_REMAP,		/* IOMMU supports interrupt isolation */
 	IOMMU_CAP_NOEXEC,		/* IOMMU_NOEXEC flag */
+	IOMMU_CAP_VIOMMU_HINT,		/* IOMMU can detect a hit for running in
+					   VM */
 };
 
 /*
-- 
2.7.4


  parent reply	other threads:[~2021-02-26 20:14 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-26 20:11 [Patch V2 00/13] Introduce dev-msi and interrupt message store Megha Dey
2021-02-26 20:11 ` [Patch V2 01/13] x86/irq: Add DEV_MSI allocation type Megha Dey
2021-02-26 20:11 ` [Patch V2 02/13] x86/msi: Rename and rework pci_msi_prepare() to cover non-PCI MSI Megha Dey
2021-02-26 20:11 ` [Patch V2 03/13] platform-msi: Provide default irq_chip:: Ack Megha Dey
2021-02-26 20:11 ` [Patch V2 04/13] genirq/proc: Take buslock on affinity write Megha Dey
2021-02-26 20:11 ` [Patch V2 05/13] genirq/msi: Provide and use msi_domain_set_default_info_flags() Megha Dey
2021-02-26 20:11 ` [Patch V2 06/13] platform-msi: Add device MSI infrastructure Megha Dey
2021-02-26 20:11 ` [Patch V2 07/13] irqdomain/msi: Provide msi_alloc/free_store() callbacks Megha Dey
2021-03-25 17:08   ` Marc Zyngier
2021-03-25 18:44     ` Thomas Gleixner
2021-03-26 10:14       ` Marc Zyngier
2021-02-26 20:11 ` [Patch V2 08/13] genirq: Set auxiliary data for an interrupt Megha Dey
2021-03-25 17:23   ` Marc Zyngier
2021-03-25 18:59     ` Thomas Gleixner
2021-03-26 10:32       ` Marc Zyngier
2021-03-26 15:09         ` Thomas Gleixner
2021-02-26 20:11 ` [Patch V2 09/13] iommu/vt-d: Add DEV-MSI support Megha Dey
2021-02-26 20:11 ` Megha Dey [this message]
2021-02-26 20:11 ` [Patch V2 11/13] platform-msi: Add platform check for subdevice irq domain Megha Dey
2021-02-26 20:11 ` [Patch V2 12/13] irqchip: Add IMS (Interrupt Message Store) driver Megha Dey
2021-03-25 17:43   ` Marc Zyngier
2021-03-25 19:07     ` Thomas Gleixner
2021-03-26  1:03       ` Dey, Megha
2021-02-26 20:11 ` [Patch V2 13/13] genirq/msi: Provide helpers to return Linux IRQ/dev_msi hw IRQ number Megha Dey
2021-03-25 17:53   ` Marc Zyngier
2021-03-26  1:02     ` Dey, Megha
2021-03-26 12:58       ` Marc Zyngier
2021-03-30  1:57         ` Dey, Megha

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1614370277-23235-11-git-send-email-megha.dey@intel.com \
    --to=megha.dey@intel.com \
    --cc=alex.williamson@redhat.com \
    --cc=ashok.raj@intel.com \
    --cc=baolu.lu@linux.intel.com \
    --cc=bhelgaas@google.com \
    --cc=dan.j.williams@intel.com \
    --cc=dave.jiang@intel.com \
    --cc=dwmw@amazon.co.uk \
    --cc=iommu@lists.linux-foundation.org \
    --cc=jgg@mellanox.com \
    --cc=joro@8bytes.org \
    --cc=kevin.tian@intel.com \
    --cc=kvm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=maz@kernel.org \
    --cc=ravi.v.shankar@intel.com \
    --cc=tglx@linutronix.de \
    --cc=tony.luck@intel.com \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).