From: Dan Williams <dan.j.williams@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
hch@lst.de, linux-acpi@vger.kernel.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v4 6/8] cxl/Kconfig: Default drivers to CONFIG_CXL_BUS
Date: Thu, 13 May 2021 22:22:16 -0700 [thread overview]
Message-ID: <162096973632.1865304.16599632599441411175.stgit@dwillia2-desk3.amr.corp.intel.com> (raw)
In-Reply-To: <162096970332.1865304.10280028741091576940.stgit@dwillia2-desk3.amr.corp.intel.com>
CONFIG_CXL_BUS is default 'n' as expected for new functionality. When
that is enabled do not make the end user hunt for all the expected
sub-options to enable. For example CONFIG_CXL_BUS without CONFIG_CXL_MEM
is an odd/expert configuration, so is CONFIG_CXL_MEM without
CONFIG_CXL_ACPI (on ACPI capable platforms). Default CONFIG_CXL_MEM and
CONFIG_CXL_ACPI to CONFIG_CXL_BUS.
Acked-by: Ben Widawsky <ben.widawsky@intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162042791307.1202325.2513845748708305095.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
drivers/cxl/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
index fb282af84afd..1da7970a5e55 100644
--- a/drivers/cxl/Kconfig
+++ b/drivers/cxl/Kconfig
@@ -15,6 +15,7 @@ if CXL_BUS
config CXL_MEM
tristate "CXL.mem: Memory Devices"
+ default CXL_BUS
help
The CXL.mem protocol allows a device to act as a provider of
"System RAM" and/or "Persistent Memory" that is fully coherent
@@ -54,6 +55,7 @@ config CXL_MEM_RAW_COMMANDS
config CXL_ACPI
tristate "CXL ACPI: Platform Support"
depends on ACPI
+ default CXL_BUS
help
Enable support for host managed device memory (HDM) resources
published by a platform's ACPI CXL memory layout description.
next prev parent reply other threads:[~2021-05-14 5:22 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-14 5:21 [PATCH v4 0/8] CXL Port Enumeration and Plans for v5.14 Dan Williams
2021-05-14 5:21 ` [PATCH v4 1/8] cxl/mem: Move some definitions to mem.h Dan Williams
2021-05-14 5:21 ` [PATCH v4 2/8] cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices Dan Williams
2021-05-14 5:22 ` [PATCH v4 3/8] cxl/core: Rename bus.c to core.c Dan Williams
2021-05-14 5:22 ` [PATCH v4 4/8] cxl/core: Refactor CXL register lookup for bridge reuse Dan Williams
2021-05-14 5:22 ` [PATCH v4 5/8] cxl/acpi: Introduce ACPI0017 driver and cxl_root Dan Williams
2021-05-14 9:17 ` Jonathan Cameron
2021-05-14 20:29 ` Dan Williams
2021-05-14 21:37 ` [PATCH v5 " Dan Williams
2021-05-14 5:22 ` Dan Williams [this message]
2021-05-14 5:22 ` [PATCH v4 7/8] cxl/port: Introduce cxl_port objects Dan Williams
2021-05-14 22:54 ` [PATCH v5 " Dan Williams
2021-05-14 5:22 ` [PATCH v4 8/8] cxl/acpi: Add module parameters to stand in for ACPI tables Dan Williams
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