From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
To: "Rob Herring" <robh@kernel.org>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: dwc: Fix integrated MSI Receiver mask reg setting during resume
Date: Wed, 2 Mar 2022 10:37:08 +0000 [thread overview]
Message-ID: <164621741211.30934.17302961993458445211.b4-ty@arm.com> (raw)
In-Reply-To: <20211226074019.2556-1-jszhang@kernel.org>
On Sun, 26 Dec 2021 15:40:19 +0800, Jisheng Zhang wrote:
> If the host which makes use of the IP's integrated MSI Receiver losts
> power during suspend, we call dw_pcie_setup_rc() to reinit the RC. But
> dw_pcie_setup_rc() always set the pp->irq_mask[ctrl] as ~0, so the mask
> register is always set as 0xffffffff incorrectly, thus the MSI can't
> work after resume.
>
> Fix this issue by moving pp->irq_mask[ctrl] initialization to
> dw_pcie_host_init(), so we can correctly set the mask reg during both
> boot and resume.
>
> [...]
Applied to pci/dwc, thanks!
[1/1] PCI: dwc: Fix integrated MSI Receiver mask reg setting during resume
https://git.kernel.org/lpieralisi/pci/c/84edd0090e
Thanks,
Lorenzo
prev parent reply other threads:[~2022-03-02 10:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-26 7:40 [PATCH] PCI: dwc: Fix integrated MSI Receiver mask reg setting during resume Jisheng Zhang
2022-01-10 3:21 ` Hongxing Zhu
2022-01-23 12:02 ` Jisheng Zhang
2022-02-23 11:46 ` Lorenzo Pieralisi
2022-02-23 16:06 ` Jisheng Zhang
2022-02-24 14:08 ` Lorenzo Pieralisi
2022-02-26 9:15 ` Jisheng Zhang
2022-03-02 10:37 ` Lorenzo Pieralisi [this message]
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