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From: Rohit Agarwal <quic_rohiagar@quicinc.com>
To: agross@kernel.org, andersson@kernel.org,
	konrad.dybcio@linaro.org, lee@kernel.org, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, mani@kernel.org,
	lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com,
	manivannan.sadhasivam@linaro.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	Rohit Agarwal <quic_rohiagar@quicinc.com>
Subject: [PATCH v3 2/5] ARM: dts: qcom: sdx65: Add support for PCIe PHY
Date: Wed,  8 Mar 2023 19:05:29 +0530	[thread overview]
Message-ID: <1678282532-16635-3-git-send-email-quic_rohiagar@quicinc.com> (raw)
In-Reply-To: <1678282532-16635-1-git-send-email-quic_rohiagar@quicinc.com>

Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is
used by the PCIe EP controller.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
 arch/arm/boot/dts/qcom-sdx65.dtsi | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 192f9f9..084daf8 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -293,6 +293,37 @@
 			status = "disabled";
 		};
 
+		pcie_phy: phy@1c06000 {
+			compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
+			reg = <0x01c06000 0x2000>;
+
+			clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
+				 <&gcc GCC_PCIE_CFG_AHB_CLK>,
+				 <&gcc GCC_PCIE_0_CLKREF_EN>,
+				 <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
+				 <&gcc GCC_PCIE_PIPE_CLK>;
+			clock-names = "aux",
+				      "cfg_ahb",
+				      "ref",
+				      "rchng",
+				      "pipe";
+
+			resets = <&gcc GCC_PCIE_PHY_BCR>;
+			reset-names = "phy";
+
+			assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
+			assigned-clock-rates = <100000000>;
+
+			power-domains = <&gcc PCIE_GDSC>;
+
+			#clock-cells = <0>;
+			clock-output-names = "pcie_pipe_clk";
+
+			#phy-cells = <0>;
+
+			status = "disabled";
+		};
+
 		tcsr_mutex: hwlock@1f40000 {
 			compatible = "qcom,tcsr-mutex";
 			reg = <0x01f40000 0x40000>;
-- 
2.7.4


  parent reply	other threads:[~2023-03-08 13:38 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-08 13:35 [PATCH v3 0/5] Add PCIe EP support for SDX65 Rohit Agarwal
2023-03-08 13:35 ` [PATCH v3 1/5] dt-bindings: PCI: qcom: Add SDX65 SoC Rohit Agarwal
2023-03-08 13:35 ` Rohit Agarwal [this message]
2023-03-08 13:35 ` [PATCH v3 3/5] ARM: dts: qcom: sdx65: Add support for PCIe EP Rohit Agarwal
2023-03-08 13:35 ` [PATCH v3 4/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe PHY Rohit Agarwal
2023-03-08 13:35 ` [PATCH v3 5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP Rohit Agarwal

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