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From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: "Pali Rohár" <pali@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Bjorn Helgaas <helgaas@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Rob Herring <robh@kernel.org>, Jingoo Han <jingoohan1@gmail.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Marc Zyngier <maz@kernel.org>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	Jassi Brar <jaswinder.singh@linaro.org>,
	Masami Hiramatsu <masami.hiramatsu@linaro.org>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v8 3/3] PCI: uniphier: Add misc interrupt handler to invoke PME and AER
Date: Fri, 23 Jul 2021 15:59:12 +0900	[thread overview]
Message-ID: <17c6eeee-692f-2e9a-5827-34f6939a21a6@socionext.com> (raw)
In-Reply-To: <20210722172627.i4n65lrz3j7pduiz@pali>

Hi Pali,

On 2021/07/23 2:26, Pali Rohár wrote:
> On Friday 23 July 2021 01:54:10 Kunihiko Hayashi wrote:
>> On 2021/07/18 9:51, Pali Rohar wrote:
>>>>> IMO this should be modelled with a separate IRQ domain and chip for
>>>>> the root port (yes this implies describing the root port in the dts
>>>>> file with a separate msi-parent).
>>>>>
>>>>> This series as it stands is a kludge.
>>>>
>>>> I see. However I need some time to consider the way to separate IRQ domain.
>>>> Is there any idea or example to handle PME/AER with IRQ domain?
>>>
>>> Seems that you are dealing with very similar issues as me with aardvark
>>> driver.
>>>
>>> As an inspiration look at my aardvark patch which setup separate IRQ
>>> domain for PME, AER and HP interrupts:
>>> https://lore.kernel.org/linux-pci/20210506153153.30454-32-pali@kernel.org/
>>>
>>> Thanks to custom driver map_irq function, it is not needed to describe
>>> root port with separate msi-parent in DTS.
>>
>> I need to understand your solution, though, this might be the same situation as my driver.
> 
> I think it is very very similar as aardvark also returns zero as hw irq
> number (and it is not possible to change it).
> 
> So simple solution for you is also to register separate IRQ domain for
> Root Port Bridge and then re-trigger interrupt with number 0 (which you
> wrote that is default) as:
> 
>      virq = irq_find_mapping(priv->irq_domain, 0);
>      generic_handle_irq(virq);
> 
> in your uniphier_pcie_misc_isr() function.

I'm not sure "register separate IRQ domain for Root Port Bridge".
Do you mean that your suggestion is to create new IRQ domain, and add this domain to root port?
Or could you show me something example?

The re-trigger part is the same method as v5 patch I wrote.

> There is no need to modify DTS. And also no need to use complicated
> logic for finding registered virq number via pcie_port_service_get_irq()
> and uniphier_pcie_port_get_irq() functions.

I see.
GIC interrupt for MSI is handled by the MSI domain by pcie-designware-host.c.
My concern is how to trigger PME/AER event with another IRQ domain.

Thank you,

---
Best Regards
Kunihiko Hayashi

  reply	other threads:[~2021-07-23  6:59 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-28  1:31 [PATCH v8 0/3] PCI: uniphier: Add PME/AER support for UniPhier PCIe host controller Kunihiko Hayashi
2020-10-28  1:31 ` [PATCH v8 1/3] PCI: portdrv: Add pcie_port_service_get_irq() function Kunihiko Hayashi
2020-11-24 23:25   ` Bjorn Helgaas
2020-10-28  1:31 ` [PATCH v8 2/3] PCI: dwc: Add msi_host_isr() callback Kunihiko Hayashi
2020-10-28  1:31 ` [PATCH v8 3/3] PCI: uniphier: Add misc interrupt handler to invoke PME and AER Kunihiko Hayashi
2020-11-24 23:20   ` Bjorn Helgaas
2020-11-25 10:23     ` Lorenzo Pieralisi
2020-11-27 12:02       ` Kunihiko Hayashi
2021-07-18  0:51         ` Pali Rohár
2021-07-22 16:54           ` Kunihiko Hayashi
2021-07-22 17:26             ` Pali Rohár
2021-07-23  6:59               ` Kunihiko Hayashi [this message]
2021-07-23  8:37                 ` Pali Rohár
2021-07-23  9:36                   ` Kunihiko Hayashi
2021-07-28  5:29                     ` Kunihiko Hayashi
2021-07-28 22:35                       ` Pali Rohár

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