From: Li Chen <me@linux.beauty>
To: "Tom Joseph" <tjoseph@cadence.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"\"Krzysztof Wilczyński\"" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci <linux-pci@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>
Subject: PCI: cadence: Allow async probe
Date: Fri, 07 Jul 2023 10:25:09 +0800 [thread overview]
Message-ID: <1892e2ae15f.f7e5dc061620757.4339091752690983066@linux.beauty> (raw)
In-Reply-To:
From: Li Chen <lchen@ambarella.com>
I observed that on Ambarella SoC, which also utilizes
the Cadence controller, the boot time increases by 1
second when no endpoints (including switch) are connected
to PCIe. This increase is caused by cdns_pcie_host_wait_for_link.
Enabling async probe can eliminate this boot time increase.
I guess other platforms also has this issue.
Signed-off-by: Li Chen <lchen@ambarella.com>
---
drivers/pci/controller/cadence/pcie-cadence-plat.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
index e091fef9c919..5177f18e1dfc 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
@@ -174,6 +174,7 @@ static struct platform_driver cdns_plat_pcie_driver = {
.name = "cdns-pcie",
.of_match_table = cdns_plat_pcie_of_match,
.pm = &cdns_pcie_pm_ops,
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = cdns_plat_pcie_probe,
.shutdown = cdns_plat_pcie_shutdown,
--
2.34.1
reply other threads:[~2023-07-07 2:25 UTC|newest]
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