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[89.162.31.138]) by smtp.gmail.com with ESMTPSA id bp25-20020a056512159900b0047f76a935a5sm308444lfb.137.2022.07.21.01.55.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 21 Jul 2022 01:55:33 -0700 (PDT) Message-ID: <19ccf775-cc1d-37de-bf4e-7745f0943851@linaro.org> Date: Thu, 21 Jul 2022 10:55:32 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH v4 1/5] dt-bindings: pci: Add ARTPEC-8 PCIe controller Content-Language: en-US To: wangseok.lee@samsung.com, "robh+dt@kernel.org" , "krzk+dt@kernel.org" , "kishon@ti.com" , "vkoul@kernel.org" , "linux-kernel@vger.kernel.org" , "jesper.nilsson@axis.com" , "lars.persson@axis.com" , "bhelgaas@google.com" , "linux-phy@lists.infradead.org" , "linux-pci@vger.kernel.org" , "devicetree@vger.kernel.org" , "lorenzo.pieralisi@arm.com" , "kw@linux.com" , "linux-arm-kernel@axis.com" , "kernel@axis.com" Cc: Moon-Ki Jun , Sang Min Kim , Dongjin Yang , Yeeun Kim References: <20220720055108epcms2p563c65b3de6333ccbc68386aa2471a800@epcms2p5> <20220720055436epcms2p63896ebe4e2131e3844044d0112288570@epcms2p6> From: Krzysztof Kozlowski In-Reply-To: <20220720055436epcms2p63896ebe4e2131e3844044d0112288570@epcms2p6> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 20/07/2022 07:54, Wangseok Lee wrote: > Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform > of Axis Communications and PCIe controller is designed based on Design-Ware > PCIe controller. > > Signed-off-by: Wangseok Lee > --- > v3->v4 : > -Add missing properties > > v2->v3 : > -Modify version history to fit the linux commit rule > -Remove 'Device Tree Bindings' on title > -Remove clock-names entries > -Change node name to soc from artpec8 on excamples Please rebase on newest Linux kernel or linux-next and use get_maintainers.pl script. > > v1->v2 : > -'make dt_binding_check' result improvement > -Add the missing property list > -Align the indentation of continued lines/entries > --- > .../bindings/pci/axis,artpec8-pcie-ep.yaml | 138 +++++++++++++++++++ > .../devicetree/bindings/pci/axis,artpec8-pcie.yaml | 148 +++++++++++++++++++++ > 2 files changed, 286 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml > create mode 100644 Documentation/devicetree/bindings/pci/axis,artpec8-pcie.yaml > > diff --git a/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml > new file mode 100644 > index 0000000..435e86f > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/axis,artpec8-pcie-ep.yaml > @@ -0,0 +1,138 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pci/axis,artpec8-pcie-ep.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARTPEC-8 SoC PCIe Controller > + > +maintainers: > + - Jesper Nilsson > + > +description: |+ > + This PCIe end-point controller is based on the Synopsys DesignWare PCIe IP > + and thus inherits all the common properties defined in snps,dw-pcie-ep.yaml. > + > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# > + > +properties: > + compatible: > + const: axis,artpec8-pcie-ep > + > + reg: > + items: > + - description: Data Bus Interface (DBI) registers. > + - description: Data Bus Interface (DBI2) registers. > + - description: PCIe address space region. > + > + reg-names: > + items: > + - const: dbi > + - const: dbi2 > + - const: addr_space > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: PIPE clock, used by the controller to clock the PIPE > + - description: PCIe dbi clock, ungated version > + - description: PCIe master clock, ungated version > + - description: PCIe slave clock, ungated version > + > + clock-names: > + items: > + - const: pipe > + - const: dbi > + - const: mstr > + - const: slv > + > + samsung,fsys-sysreg: > + description: > + Phandle to system register of fsys block. > + $ref: /schemas/types.yaml#/definitions/phandle Since you wrote this is one register, I expect offset: https://elixir.bootlin.com/linux/v5.18-rc1/source/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml#L42 > + > + samsung,syscon-phandle: > + description: > + Phandle to the PMU system controller node. > + $ref: /schemas/types.yaml#/definitions/phandle > + > + samsung,fsys-bus-s: > + description: > + Phandle to bus-s of fsys block, this register > + is additional control sysreg in fsys block and > + this is used for pcie slave control setting. > + $ref: /schemas/types.yaml#/definitions/phandle Ditto > + > + samsung,fsys-bus-p: > + description: > + Phandle to bus-p of fsys block, this register > + is additional control sysreg in fsys block and > + this is used for pcie dbi control setting. > + $ref: /schemas/types.yaml#/definitions/phandle Ditto > + > + phys: > + maxItems: 1 > + > + phy-names: > + items: > + - const: pcie_phy > + > + num-lanes: > + const: 2 > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - interrupt-names > + - clocks > + - clock-names > + - samsung,fsys-sysreg > + - samsung,syscon-phandle > + - samsung,syscon-bus-s-fsys This does not match what you wrote in properties. Best regards, Krzysztof