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From: Thierry Reding <thierry.reding@avionic-design.de>
To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Andrew Murray <andrew.murray@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Arnd Bergmann <arnd@arndb.de>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RFC 0/2] PCI: Introduce MSI chip infrastructure
Date: Mon, 25 Mar 2013 08:58:10 +0100	[thread overview]
Message-ID: <20130325075810.GA28935@avionic-0098.mockup.avionic-design.de> (raw)
In-Reply-To: <20130324120649.6fb8c05d@skate>

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On Sun, Mar 24, 2013 at 12:06:49PM +0100, Thomas Petazzoni wrote:
> Andrew, Thierry,
> 
> On Fri, 22 Mar 2013 09:30:27 +0000, Andrew Murray wrote:
> 
> > I think this could work well. In the future if the use of an independent MSI
> > controller is required, then new DT bindings for host-bridges could use
> > phandles to reference independent MSI controllers as their providers of
> > MSIs. I guess this functionality can be built on top of what you have proposed
> > later as the need arises.
> 
> On Marvell HW (at least Armada 370/XP), MSIs are handled by the
> main interrupt controller directly, or more precisely, managing the
> MSIs requires fiddling with registers that are part of the interrupt
> controller registers, and not part of the PCIe controller registers.
> 
> Basically, when a MSI interrupt is raised, it corresponds to IRQ 1 on
> the main interrupt controller. Then, one has to read a register of the
> main interrupt controller to find out which MSI interrupt was actually
> triggered. So in our case, the MSI irq_chip really belongs to the
> interrupt controller driver, and not the PCIe driver. Also, the
> physical address to be added in the 'struct msi_msg' is the physical
> address of an interrupt controller register.
> 
> Therefore, I'm not sure how to do the interaction between the PCIe
> driver and the interrupt controller driver.
> 
> Suggestions?

That sounds very much like one of the use-cases that were discussed. The
easiest solution would probably be to add an API to look up an MSI chip
from a DT phandle, so that the PCIe controller's device node could have
it as a property, somewhat like this:

	msi: interrupt-controller {
	};

	pcie-controller {
		...
		marvell,msi = <&msi>;
		...
	};

Then add some basic infrastructure to register the MSI chip with a
global list, call that from the interrupt controller initialization:

	...
	msi_chip_add(&msi);
	...

And finally look it up from the PCIe controller driver:

	node = of_parse_phandle(dev->of_node, "marvell,msi", 0);
	if (node)
		msi = of_find_msi_chip_by_node(node);

That's roughly what other subsystems do. I wrote something similar once
for backlight devices, though the registration step (msi_chip_add)
wasn't necessary there since backlight devices all go into a common
struct class so class_find_device() can be used instead of going through
a separate registry.

Thierry

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  reply	other threads:[~2013-03-25  7:58 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-22  8:51 [RFC 0/2] PCI: Introduce MSI chip infrastructure Thierry Reding
2013-03-22  8:51 ` [RFC 1/2] PCI: Introduce new " Thierry Reding
2013-03-22  9:37   ` Andrew Murray
2013-03-22 10:00     ` Thierry Reding
2013-03-22  8:51 ` [RFC 2/2] PCI: tegra: Use " Thierry Reding
2013-03-25 17:01   ` Stephen Warren
2013-03-25 20:02     ` Thierry Reding
2013-03-22  9:30 ` [RFC 0/2] PCI: Introduce " Andrew Murray
2013-03-24 11:06   ` Thomas Petazzoni
2013-03-25  7:58     ` Thierry Reding [this message]
2013-03-25  8:38       ` Thomas Petazzoni
2013-03-25  9:15         ` Thierry Reding
2013-03-25  9:29           ` Arnd Bergmann

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