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From: Thierry Reding <thierry.reding@avionic-design.de>
To: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Andrew Murray <andrew.murray@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Arnd Bergmann <arnd@arndb.de>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RFC 0/2] PCI: Introduce MSI chip infrastructure
Date: Mon, 25 Mar 2013 10:15:34 +0100	[thread overview]
Message-ID: <20130325091534.GA21054@avionic-0098.mockup.avionic-design.de> (raw)
In-Reply-To: <20130325093847.7474dc0e@skate>

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On Mon, Mar 25, 2013 at 09:38:47AM +0100, Thomas Petazzoni wrote:
> Dear Thierry Reding,
> 
> Thanks for your feedback!
> 
> On Mon, 25 Mar 2013 08:58:10 +0100, Thierry Reding wrote:
> 
> > That sounds very much like one of the use-cases that were discussed. The
> > easiest solution would probably be to add an API to look up an MSI chip
> > from a DT phandle, so that the PCIe controller's device node could have
> > it as a property, somewhat like this:
> > 
> > 	msi: interrupt-controller {
> > 	};
> > 
> > 	pcie-controller {
> > 		...
> > 		marvell,msi = <&msi>;
> > 		...
> > 	};
> 
> I'm not sure how to handle this msi interrupt controller with the main
> interrupt controller. For now, I have:
> 
>         mpic: interrupt-controller@d0020000 {
>               reg = <0xd0020a00 0x2d0>,
>                     <0xd0021070 0x58>;
>         };
> 
> 	[...]
> 
> 	soc {
>                 interrupt-parent = <&mpic>;
> 		[...]
> 	};
> 
> And the MSI interrupt controller shares the same registers as the MPIC.
> So should it be something like:
> 
> 	interrupt-controller {
> 		reg = <0xd0020a00 0x2d0>,
>                     <0xd0021070 0x58>;
> 
> 		mpic {
> 			/* Not sure what to have here */
> 		};
> 
> 		msi {
> 
> 			/* Here either */
> 		};
> 	};
> 
> 	soc {
>                 interrupt-parent = <&mpic>;
> 
> 		pcie-controller {
> 			marvell,msi = <&msi>;
> 		};
> 	};
> 
> Or some other idea?

I think you can just make this:

	mpic: interrupt-controller@d0020000 {
		...
	};

	...

	soc {
		pcie-controller {
			marvell,msi = <&mpic>;
		};
	};

And everything else should just work given the APIs I mentioned. But as
you said it'd be good if somebody else could share their opinion about
this.

Thierry

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  reply	other threads:[~2013-03-25  9:15 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-03-22  8:51 [RFC 0/2] PCI: Introduce MSI chip infrastructure Thierry Reding
2013-03-22  8:51 ` [RFC 1/2] PCI: Introduce new " Thierry Reding
2013-03-22  9:37   ` Andrew Murray
2013-03-22 10:00     ` Thierry Reding
2013-03-22  8:51 ` [RFC 2/2] PCI: tegra: Use " Thierry Reding
2013-03-25 17:01   ` Stephen Warren
2013-03-25 20:02     ` Thierry Reding
2013-03-22  9:30 ` [RFC 0/2] PCI: Introduce " Andrew Murray
2013-03-24 11:06   ` Thomas Petazzoni
2013-03-25  7:58     ` Thierry Reding
2013-03-25  8:38       ` Thomas Petazzoni
2013-03-25  9:15         ` Thierry Reding [this message]
2013-03-25  9:29           ` Arnd Bergmann

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